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4,502 Commits 5 Branches 63 Tags
478c76c1cae2ae90c33fa7fed7d3d68ef68c656c
Commit Graph
621 Commits
Author SHA1 Message Date
Sam Crow 478c76c1ca get connections from spice objects in instances 2023-07-18 10:50:50 -07:00
Sam Crow 8a441bc68b Merge branch 'dev' into STA-refactor 2023-07-17 16:35:31 -07:00
Sam Crow 45b88889e4 use pin and net objects in connect_inst 2023-07-17 16:04:56 -07:00
Sam Crow d0339a90e6 change spice_nets and spice_pins to dicts 2023-07-17 15:36:57 -07:00
Sam Crow e15feb2361 change nets list to dictionary 2023-07-17 15:36:22 -07:00
Sam Crow 7581df2255 change pins to OrderedDict 2023-07-17 15:22:35 -07:00
Sam Crow c8c43f75d9 add spice nets and a way to connect them to pins 2023-07-14 16:18:10 -07:00
Sam Crow 146efc5070 implement pin_spice object 2023-07-13 16:45:05 -07:00
Sam Crow 89d8441108 Merge branch 'dev' into delay_ctrl 2023-07-10 14:31:26 -07:00
Sam Crow 4e649aad6b fix typo bug in spice comments code 2023-07-10 13:21:24 -07:00
Sam Crow b91c628acf Merge branch 'dev' into delay_ctrl 2023-07-06 08:45:03 -07:00
Sam Crow 91694fdae3 add fixme note for unit conversion 2023-06-28 14:05:42 -07:00
Gary Mejia 9a36cce7ae Fixed formatting on all files 2023-06-14 12:28:36 -07:00
Gary Mejia a3284e8b47 Fixed module from writing syntax issues 2023-06-13 17:30:38 -07:00
Gary Mejia 692acd2066 Verilog ROM model created for testing 2023-06-12 15:35:54 -07:00
Jacob Walker fef9902c45 rom base passing tests with top level routing 2023-03-30 11:30:50 -07:00
Jacob Walker af0209ec96 passing code style 2023-03-30 11:30:50 -07:00
Jacob Walker bbf2cd2913 Changes for test generation and simulation 2023-03-30 11:30:50 -07:00
Jacob Walker f7aed247fd column control and address precharge 2023-03-30 11:30:50 -07:00
samuelkcrow 3a8e29ce77 Merge remote-tracking branch 'origin/dev' into no_rbl 2023-02-20 22:11:02 -08:00
Eren Dogan e5fc25da6f Update copyright year 2023-01-28 22:56:27 -08:00
samuelkcrow 29c79abaf8 move layout pins when copying them 2023-01-15 20:33:38 -08:00
mrg 7ddb1a39dc Line wrap output spice subckt and instance lines at 80 characters. 2022-12-12 13:58:30 -08:00
Eren Dogan 96e57507bf Add copyright check to code format test 2022-11-30 14:50:43 -08:00
Eren Dogan 2e7206343e Remove unnecessary imports 2022-11-27 13:11:10 -08:00
Eren Dogan fccdc3c45b Use library imports globally 2022-11-27 13:01:20 -08:00
Bugra Onal 25cc08db80 Further fixes for new verilog naming convention 2022-08-18 11:03:13 -07:00
Bugra Onal aefe46394c Merge branch 'dev' into multibank 2022-08-12 21:45:26 -07:00
Bugra Onal a361d9f7bb Fixed write_size checks for None 2022-07-28 16:45:58 -07:00
Bugra Onal c1e891b2fb Multibank file generation (messy) 2022-07-28 15:03:41 -07:00
Bugra Onal 846dfc79dc modified template engine & sram multibank class 2022-07-28 15:03:41 -07:00
Bugra Onal bde4a389aa Template section clone method 2022-07-28 15:03:41 -07:00
Bugra Onal 9158e92a71 TEmplate rework 2022-07-28 15:03:41 -07:00
Bugra Onal a5728cdecc Base-verilog 2022-07-28 15:03:41 -07:00
Bugra Onal 769633a459 Base template additions 2022-07-28 15:03:41 -07:00
Bugra Onal cda3822526 Verilog Template additions 2022-07-28 15:03:41 -07:00
Bugra Onal 28c5406075 Base verilog template init 2022-07-28 15:03:41 -07:00
Bugra Onal 30f5638b9f Replaced instances of addr_size with bank_addr 2022-07-28 15:03:41 -07:00
Bugra Onal 24bb6f8c11 Multibank file generation (messy) 2022-07-28 15:03:37 -07:00
mrg 5db470155e Fix print errors in code format unit test. 2022-07-26 12:20:15 -07:00
Eren Dogan e3fe8c3229 Remove line ending whitespace 2022-07-22 19:52:38 +03:00
Bugra Onal 6d6063ef4e modified template engine & sram multibank class 2022-07-21 15:56:29 -07:00
Bugra Onal b75e1fc499 Template section clone method 2022-07-21 15:45:50 -07:00
Bugra Onal f2cd611cb8 TEmplate rework 2022-07-21 15:45:50 -07:00
Bugra Onal 988399ba73 Base-verilog 2022-07-21 15:45:50 -07:00
Bugra Onal 06c56c256e Base template additions 2022-07-21 15:45:50 -07:00
Bugra Onal 3d3a8202fe Verilog Template additions 2022-07-21 15:45:50 -07:00
Bugra Onal be9fadf1bb Base verilog template init 2022-07-21 15:45:50 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 8217a84165 Uniquify overlap points during segment overlap computation. 2022-05-17 13:31:23 -07:00