Bugra Onal 28c5406075 Base verilog template init

2022-07-28 15:03:41 -07:00

..

__init__.py

Use packages for imports.

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channel_route.py

Use packages for imports.

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contact.py

Use packages for imports.

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delay_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

design.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

errors.py

Add exception errors file

2020-04-08 16:55:45 -07:00

geometry.py

Use packages for imports.

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hierarchy_design.py

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hierarchy_layout.py

Use packages for imports.

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hierarchy_spice.py

Use packages for imports.

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lef.py

Use packages for imports.

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logical_effort.py

Use packages for imports.

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pin_layout.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

power_data.py

Update copyright year.

2021-01-22 11:23:28 -08:00

route.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

timing_graph.py

Added SA parameters for CACTI delay. Fixed syntax issues in several modules. Fixed issue with slew not being propogated to the next delay stage.

2021-09-07 15:56:27 -07:00

utils.py

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2022-07-13 15:55:57 -07:00

vector3d.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

vector.py

Fix missing hash recompute in vector class.

2022-05-17 13:30:41 -07:00

verilog.py

Replaced instances of addr_size with bank_addr

2022-07-28 15:03:41 -07:00

verilog.v

Base verilog template init

2022-07-28 15:03:41 -07:00

wire_path.py

Use packages for imports.

2022-07-13 15:55:57 -07:00

wire_spice_model.py

Added unit r and c values with m2 minwidth incorporated to match CACTI params

2021-08-01 00:23:59 -07:00

wire.py

Use packages for imports.

2022-07-13 15:55:57 -07:00