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OpenRAM
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67 Commits

Author SHA1 Message Date
mrg 2adab1ea1a Initial work on separate delay and func simulation 2022-08-10 12:14:47 -07:00
mrg 28128157c0 Initial work on separate delay and func simulation 2022-08-10 12:06:14 -07:00
mrg d92c7a634d Use packages for imports. 
Must set PYTHONPATH to include OPENRAM_HOME now.
Reorganizes subdirs as packages.
Rewrites unit tests to use packages.
Update README.md with instructions, dependencies etc.
Update sky130 module imports.
Change tech specific package from modules to custom.
 2022-07-13 15:55:57 -07:00
mrg 64f2f90664 Rework replica_bitcell_array supplies 
Uses layer and direction preferences in tech file.
Places straps on left/right or top/bottom.
 2022-04-19 08:50:11 -07:00
mrg 229a3b5b3d By default uniquify instances based on macro name. 2022-03-11 18:01:45 -08:00
Matt Guthaus 30fc81a1f0 Update copyright year. 2021-01-22 11:23:28 -08:00
mrg da721a677d Remove EOL whitespace globally 2020-11-03 06:29:17 -08:00
mrg a3195c0827 Add words_per_row and others in config file. 2020-07-13 12:37:56 -07:00
mrg 282f944b2f Also write .lvs file since it can be different the .sp 2020-07-03 06:55:35 -07:00
Aditi Sinha 88bc1f09cb Characterization for extra rows 2020-02-20 17:01:52 +00:00
Matt Guthaus abd8b0a23a Only setup bitcell when running top-level OpenRAM 2019-11-26 13:54:37 -08:00
mrg d583695959 Remove some flake8 errors/warnings. 2019-10-02 23:26:02 +00:00
Matt Guthaus 69c5608b53 Allow gds to be written with supplies off. Fix extraction bug with new options. 2019-09-03 11:23:35 -07:00
jsowash 1f76afd294 Begin wmask functionality. Added wmask to verilog file and config parameters. 2019-06-28 15:43:09 -07:00
Matt Guthaus a234b0af88 Fix space before comment 2019-06-14 08:43:41 -07:00
Matt Guthaus 0f03553689 Update copyright to correct years. 2019-05-06 06:50:15 -07:00
Matt Guthaus 3f9a987e51 Update copyright. Add header to all OpenRAM files. 2019-04-26 12:33:53 -07:00
Matt Guthaus c3e074c069 Add option for routing supplies. Off by default, but enabled in unit test config files. 2019-04-01 09:58:59 -07:00
Jesse Cirimelli-Low 87380a4801 complete log file generation 2019-01-13 14:34:46 -08:00
Matt Guthaus 5de7ff3773 Updated Verilog to have multiport. Added 1rw,1rw/1r Verilog testbench. 2019-01-11 14:15:16 -08:00
Jesse Cirimelli-Low e58515b89b tables stable and flask removed, headers are bugged 2019-01-08 19:50:47 -08:00
Matt Guthaus b15584a821 Print start time after banner and init 2018-12-07 15:50:18 -08:00
Jesse Cirimelli-Low 3d9203a7ea Merge branch 'dev' into datasheet_gen 2018-12-07 04:29:07 -08:00
Matt Guthaus 46d3068821 Output number of words per row before SRAM creation. Recompute words per row in unit tests. 2018-12-06 13:11:47 -08:00
Jesse Cirimelli-Low cd0e763895 moved system call to datasheet.info generator 2018-12-05 17:35:35 -08:00
Jesse Cirimelli-Low 7e475b376e switch to git rev-parse solution for id parsing 2018-12-05 14:58:37 -08:00
Jesse Cirimelli-Low ce5001e0af added config file to datasheet and output files 2018-10-31 12:29:13 -07:00
Matt Guthaus 7591f25a2e Merge branch 'dev' into supply_routing 2018-10-20 14:29:19 -07:00
Jesse Cirimelli-Low b9990609bf provides warning on missing flask packages, does not generate html on missing packages 2018-10-18 07:21:03 -07:00
Matt Guthaus 1c426aad29 Merge remote-tracking branch 'origin/datasheet_gen' into supply_routing 2018-10-12 20:55:57 -07:00
Jesse Cirimelli-Low afba54a22d added analytical model support, added proper output with sram.py 2018-10-12 13:22:12 -07:00
Jesse Cirimelli-Low cfb5921d98 reorganized code structure 2018-10-11 15:59:06 -07:00
Jesse Cirimelli-Low bc54bc238f removed tabs and fixed bug in which datasheets generated without the characterizer running 2018-10-11 11:18:40 -07:00
Jesse Cirimelli-Low 49268b025f fixed /tmp/ typo 2018-10-06 21:17:26 -07:00
Jesse Cirimelli-Low fa979e2d34 initial stages of html documentation generation 2018-10-06 21:15:54 -07:00
Matt Guthaus 7432192e5e Small change to test webhook 2018-09-24 09:11:44 -07:00
Matt Guthaus 922e3f4c13 Small change to test webhook 2018-09-21 15:05:46 -07:00
Matt Guthaus ade12c9dc2 Small change to test webhook 2018-09-21 15:03:16 -07:00
Matt Guthaus e1864a7a1e Small change to test webhook 2018-09-21 15:02:16 -07:00
Matt Guthaus 2b3b4bbee6 Small change to test webhook 2018-09-21 15:01:07 -07:00
Matt Guthaus a346bddd88 Cleanup some items with new sram_config. Update unit tests accordingly. 2018-09-04 10:47:24 -07:00
Matt Guthaus 563ff77d44 Add sram_config class. Rename port variables for better description. 2018-08-31 12:03:28 -07:00
Matt Guthaus 9f051df18d Added netlist only configuration option. 2018-08-27 14:33:02 -07:00
Matt Guthaus a4c29ea527 Improve openram output. Fix save output function name. 2018-07-12 10:35:38 -07:00
Matt Guthaus f34c4eb7dc Convert entire OpenRAM to use python3. Works with Python 3.6. 
Major changes:
Remove mpmath library and use numpy instead.
Convert bytes to new bytearrays.
Fix class name check for duplicate gds instances.
Add explicit integer conversion from floats.
Fix importlib reload from importlib library
Fix new key/index syntax issues.
Fix filter and map conversion to lists.
Fix deprecation warnings.
Fix Circuits vs Netlist in Magic LVS results.
Fix file closing warnings.
 2018-05-14 16:15:45 -07:00
Matt Guthaus a732405836 Add utility script gen_stimulus.py to help create simulations for debugging. 2018-02-26 08:54:35 -08:00
mguthaus 5aa92a6549 Reorganize top-level functions a bit more. Add help info to banner. 2018-02-09 09:53:28 -08:00
Matt Guthaus 17716191c1 Clean up time statements in openram output 2018-02-08 13:11:18 -08:00
Matt Guthaus 6c89f7965d Refactor openram.py. 2018-02-08 12:47:19 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00