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OpenRAM
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870 Commits

Author SHA1 Message Date
Matt Guthaus a56fa0e787 Fix wrong pin order on pnand2 LVS problem. 2018-01-29 15:31:14 -08:00
Matt Guthaus 8fcc8a1674 Increase height slightlty to allow pnand3 to pass DRC. 2018-01-29 15:30:58 -08:00
Matt Guthaus 79715ae1a2 Fix input discrepencies in pre3x8 2018-01-29 15:25:41 -08:00
Matt Guthaus 3c5ecb963d Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:15 -08:00
Matt Guthaus 586d80623e Remove level of indirection to ptx devices to allow LVS symmetries. 2018-01-29 15:25:00 -08:00
Michael Timothy Grimes fb2572bd71 Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport 2018-01-28 21:44:22 -08:00
Matt Guthaus 31c192c2e9 Fix precharge nwell contact spacing DRC violatin. 2018-01-26 13:53:45 -08:00
Matt Guthaus e46a4fb115 Use any spice for the functional tests. 2018-01-26 13:53:11 -08:00
Matt Guthaus 028146f3c2 Add output explaining error for not finding simulator in unit tests. 2018-01-26 13:23:11 -08:00
Matt Guthaus 369aa85cd2 Fail simulation tests if correct spice is not found. Correctly load spice characterizer. 2018-01-26 13:00:25 -08:00
Matt Guthaus 50107636a0 Fail test early if spice simulator is not found. 2018-01-26 12:47:32 -08:00
Matt Guthaus 1dc7752429 Fix 6T and replica cell contact spacing issues with Magic DRC. 
DRC/LVS passing for all parameterized gates.
Magic and GDS match for SCMOS rules again.
 2018-01-26 12:39:00 -08:00
Matt Guthaus fb0355ebaf Duplicate gnd label on metal1 pin in tri gate. 2018-01-24 13:20:34 -08:00
Matt Guthaus 039f531243 Capitalize bitline labels in write driver 2018-01-24 13:15:14 -08:00
Matt Guthaus d84242719b Change pin names in trigate and write_driver. 2018-01-24 13:12:36 -08:00
Matt Guthaus ac8eada0d8 Fix devices sizes in SCMOS sense amp. Elaborate magic/netgen scripts in comments. 2018-01-24 13:02:55 -08:00
Matt Guthaus 1b2df3a5a1 Properly ignore ad as, pd, ps property errors 2018-01-22 17:50:53 -08:00
Matt Guthaus 2468f224d9 SCMOS library cells passing LVS (with property errors though). Permute must be enabled before compare, duh. 2018-01-22 17:14:39 -08:00
Matt Guthaus fb2ed1d46c Add wells to fix DRC errors in SCMOS library cells. 2018-01-22 16:28:20 -08:00
Matt Guthaus f572b83671 Add Makefile for parallel test execution. 2018-01-22 13:39:07 -08:00
Matt Guthaus 10ced33127 Fixed command line arguments to take priority over config file. Any option can be specified in config file now. 2018-01-21 11:21:09 -08:00
Matt Guthaus c80a55c13d Adding old documentation. Partially updated intro and overview. It is very outdated. 2018-01-19 17:31:17 -08:00
Matt Guthaus 84ec7a5be0 Convert unit tests to use new options as well. 2018-01-19 17:23:38 -08:00
Matt Guthaus 95fab1ca71 Remove personalized temp dir. 2018-01-19 16:39:14 -08:00
Matt Guthaus 490a70dee9 Simplify configuration file to allow all options to be over-riden. Move default module types to options.py to simplify config file. 2018-01-19 16:38:19 -08:00
Matt Guthaus 72b0617e81 Merge branch 'dev' of github.com:mguthaus/OpenRAM into dev 2018-01-19 16:19:12 -08:00
Matt Guthaus efa465757c Remove dead code ptx_port. 2018-01-19 16:19:05 -08:00
Matt Guthaus fcc533ec11 Initial LVS using netgen. pinv nad pnand2 pass. No property checks in LVS yet. 2018-01-17 16:48:35 -08:00
Matt Guthaus ba489f0291 Only check if using magic with freepdk when LVSDRC is enabled. 2018-01-17 07:38:29 -08:00
Matt Guthaus 7c50708158 Check that we are not using Magic for FreePDK45. 2018-01-12 14:50:35 -08:00
Matt Guthaus 243097cb33 Remove print statement in magic.py 2018-01-12 14:45:11 -08:00
Matt Guthaus 1b30eb4b64 Initial DRC with Magic is done. 2018-01-12 14:39:42 -08:00
Matt Guthaus 7a172873a3 Update unit tests to load verify after config file. Start magic DRC. 2018-01-12 10:24:49 -08:00
Matt Guthaus e0a6b59773 Fix LEF test mismatch in regression. 2018-01-12 08:54:31 -08:00
Matt Guthaus 1701eac1a9 Added workaround to import layouts into Magic. Select and well layers in active contacts. Fixed missing implant enclose active DRC rule in parameterized cells. 2018-01-11 10:24:44 -08:00
Michael Timothy Grimes 64e7ed5b5e Adding pbitcell.py: a multiport bitcell with a variable number of write ports and read ports 
Adding 04_pbitcell_test.py: The benchtest for pbitcell

Mostly done. Layout nearly complete with the exception of the well contacts and a connection between the gates of the read
transistors and their corresponding vias. Then several drc corrections need to be made.
 2018-01-09 13:39:42 -08:00
Matt Guthaus f028436156 Add implant/select enclosure rule to ptx. 2018-01-08 12:27:50 -08:00
Matt Guthaus e95988c639 Document tech files. Remove unused/redundant rules. Made rule names consistent/simple. 2018-01-08 11:57:51 -08:00
Matt Guthaus 547746f839 Merge branch 'dev' 2018-01-05 08:34:47 -08:00
Matt Guthaus fd748b4fe4 Move info messages about modes to better locations. 2018-01-05 08:32:23 -08:00
Matt Guthaus 4885616bec Remove metal3 in LEF library cells. 2017-12-19 13:12:39 -08:00
Matt Guthaus 97a2d620fe Fix dev tests. Split pruned test to separate golden result. 2017-12-19 11:42:11 -08:00
Matt Guthaus ee7bf7c5f2 Remove metal3 blanket blockage on library cells. 2017-12-19 09:55:59 -08:00
Matt Guthaus 40465d6518 Merge tolerance change from master. 2017-12-19 09:17:43 -08:00
Matt Guthaus 9059a15ceb Remove tab in lef file. 2017-12-19 09:14:59 -08:00
Matt Guthaus 9a4b2b4341 Revised LEF and Verilog generation. Does not read GDS for speed improvements. 2017-12-19 09:01:24 -08:00
mguthaus 13902538ff Increase lib file tolerance to 25 percent. 2017-12-19 07:41:08 -08:00
mguthaus f98155fc0b Increase lib file tolerance to 25 percent. 2017-12-19 07:39:43 -08:00
Matt Guthaus 317f2d1293 Merge update master and dev. 2017-12-18 08:13:59 -08:00
Matt Guthaus a4a9205a56 Change thresholds to 50 percent. 2017-12-15 08:02:48 -08:00