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OpenRAM
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191 Commits

Author SHA1 Message Date
mguthaus 09ca8ba17d Improve output format. Rename option to be more sensible. 2017-11-22 15:57:29 -08:00
Matt Guthaus cf66c83fe4 Fixed address bug to simulate correct wordline 2017-11-21 13:57:59 -08:00
Matt Guthaus aa4768bf87 Add time info for spice simulation calls. 2017-11-21 13:04:18 -08:00
Matt Guthaus 6873342748 Prepend the config file path so it imports your local copy rather than example_config_freepdk, for example. 2017-11-20 11:57:41 -08:00
Matt Guthaus 76ea89e06f Merge branch 'magic_netgen_support' into dev 2017-11-16 13:57:18 -08:00
Matt Guthaus 88740c107f Improve global and code structure using modules. 
Comment and reorganize globals.py
Tests consistently use globals module for OPTions.
Add characterizer as module support.
Modify unit tests to reload new characterizer for ngspice/hspice.
Enable relative and absolute config file arguments so you can run
openram from anywhere on any config file.
 2017-11-16 13:52:58 -08:00
Matt Guthaus 347f1f97fd Merge branch 'master' into magic_netgen_support 2017-11-15 17:05:38 -08:00
mguthaus 2eb9f5c6bc Move verify into a module. Make characterizer a module. Move exe searching to modules. 2017-11-15 17:02:53 -08:00
Matt Guthaus 658f794b12 Add draft of assura DRC/LVS 2017-11-15 12:07:10 -08:00
Matt Guthaus f6410e0371 Merge branch 'master' into dev 2017-11-15 11:46:11 -08:00
Matt Guthaus 75a3884568 Remove tab 2017-11-15 11:45:55 -08:00
Matt Guthaus f123a3ca40 Merge branch 'master' into dev 2017-11-15 07:43:56 -08:00
Matt Guthaus 102db4fecf Fixed prune unit test by relaxing tolerance. 2017-11-15 07:43:43 -08:00
Matt Guthaus 37edd7cac6 Change unit tests to use verify instead of calibre. Debugging gds read comments in magic.py. 2017-11-14 16:24:26 -08:00
Matt Guthaus 4285e576f8 Change error to warning for magic/netgen. 2017-11-14 15:49:47 -08:00
Matt Guthaus 40410cc9f5 Clean up code to work when no drc/lvs/pex is found. 2017-11-14 15:31:58 -08:00
Matt Guthaus 257cd62d25 Remove tools from tech file and have search order preference like spice. 2017-11-14 15:27:03 -08:00
Matt Guthaus 3e0f39cd8e Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
Matt Guthaus 70ab672c5c Pad strings in GDS to even number of bytes per bug report. 2017-11-14 14:30:00 -08:00
Matt Guthaus 29c5ab48f0 Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
Matt Guthaus 8071dcc0f3 Add customsim (xa) as optional simulator. Fix regex to support scientific notation. Go through list of preferred simulators in order. Always abort if command-line simulator not found. 2017-11-12 10:42:41 -08:00
Jun Chen 054e4d3c28 my change 2017-11-11 16:54:04 +09:00
Matt Guthaus 95f1a24f72 Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
Matt Guthaus 0744cbcc60 Merge branch 'master' into dev 2017-11-09 09:11:26 -08:00
Matt Guthaus 05158f104b Removed unnecessary sram_tb.v file. 2017-10-17 15:51:31 -07:00
mguthaus 5c10aebc0f Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
Matt Guthaus 10a8531813 Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
Matt Guthaus a9797d12ab Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
Matt Guthaus b2043bef11 Fix small delay difference in unit test 21_hspice_delay_test. 2017-10-05 08:13:53 -07:00
Matt Guthaus 69e44c78d8 Upgrade version to 1.01 2017-10-04 20:18:30 -07:00
Matt Guthaus 59a0394c2b Update LEF files with modified blockages. 2017-10-04 20:17:30 -07:00
Matt Guthaus 788f3d9122 4-bank SRAMs are now working. 2017-10-04 18:05:45 -07:00
Matt Guthaus 21c77645d3 Remove LVS correspondence points for multibank in single bank. 2017-09-29 16:44:24 -07:00
Matt Guthaus e06e1691c8 Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
Matt Guthaus d29dd03373 SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
Matt Guthaus 3ea003c367 Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
Matt Guthaus d17711c394 Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
Matt Guthaus cf940fb15d Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
Matt Guthaus 857b997367 Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
Matt Guthaus d77216d6dd Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
Matt Guthaus 7ec20a72c8 Fix old unit test golden result 2017-07-06 14:16:02 -07:00
Matt Guthaus 20d8c0bc45 Improved characterizer. 2017-07-06 08:42:25 -07:00
mguthaus e92cb9ecef Removed array_type from ms_flop_array since it is extraneous code. 2017-07-03 12:08:50 -07:00
Matt Guthaus 8a821e13ac Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking. 2017-06-12 15:02:48 -07:00
mguthaus 6e90bf0d6d Enable output filename and path to be in config file. Command line will over-ride config file. 2017-06-12 14:37:15 -07:00
mguthaus a840209c08 Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
Matt Guthaus 93389ac723 Add test to reroute after route fails. Disable GDS route debug info unless verbosity is more than 0. 2017-06-07 10:10:18 -07:00
mguthaus 5960324ca6 Simplify sparse add for grid map. 2017-06-07 09:38:57 -07:00
mguthaus c061b985ba Fix missing map key check in blocked get/set. 2017-06-06 17:12:19 -07:00
Matt Guthaus 8b5e92e582 Merge branch 'master' of github.com:mguthaus/OpenRAM 2017-06-06 11:06:35 -07:00