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characterizer
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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gdsMill
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Added new scmos test with a bigger design. Added error checks for not found label and not found pin shapes.
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2017-05-24 10:50:45 -07:00 |
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router
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Fix unit tests to be DRC clean.
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2017-06-07 10:29:53 -07:00 |
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tests
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Fix old unit test golden result
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2017-07-06 14:16:02 -07:00 |
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bank.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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bitcell.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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bitcell_array.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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calibre.py
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Changed DRC and LVS results output database to end in .db instead of .results. Calibre uses file extensions to determine file type.
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2017-04-21 14:07:16 -07:00 |
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contact.py
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Removed unique id for contacts. Contact/via name, however, must distinguish types of contacts based on layers used.
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2017-04-26 10:24:51 -07:00 |
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control_logic.py
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Removed array_type from ms_flop_array since it is extraneous code.
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2017-07-03 12:08:50 -07:00 |
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debug.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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design.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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example_config_freepdk45.py
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Enable output filename and path to be in config file. Command line will over-ride config file.
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2017-06-12 14:37:15 -07:00 |
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example_config_scn3me_subm.py
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Enable output filename and path to be in config file. Command line will over-ride config file.
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2017-06-12 14:37:15 -07:00 |
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geometry.py
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Added zoom to technology file so labels in each tech are readable size. Made default size.
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2017-05-23 16:18:11 -07:00 |
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globals.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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hierarchical_decoder.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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hierarchical_predecode.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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hierarchical_predecode2x4.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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hierarchical_predecode3x8.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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hierarchy_layout.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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hierarchy_spice.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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lef.py
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RELEASE 1.0
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2016-11-08 09:57:35 -08:00 |
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logic_effort_dc.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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ms_flop.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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ms_flop_array.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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nand_2.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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nand_3.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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nor_2.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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openram.py
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Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking.
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2017-06-12 15:02:48 -07:00 |
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options.py
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Enable output filename and path to be in config file. Command line will over-ride config file.
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2017-06-12 14:37:15 -07:00 |
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path.py
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Improve debug messages. Remove add_inst for via in wire.
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2016-11-18 14:10:30 -08:00 |
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pinv.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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precharge.py
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Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.
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2017-04-26 14:33:03 -07:00 |
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precharge_array.py
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RELEASE 1.0
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2016-11-08 09:57:35 -08:00 |
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ptx.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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regress.sh
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Add regress.sh script for convenience
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2016-11-18 08:00:34 -08:00 |
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replica_bitcell.py
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RELEASE 1.0
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2016-11-08 09:57:35 -08:00 |
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replica_bitline.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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route.py
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Fixed rotated via bug. May still have a via-to-via spacing problem.
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2017-04-24 13:47:56 -07:00 |
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sense_amp.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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sense_amp_array.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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single_level_column_mux.py
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Removed the name from ptx class. Ptx name is uniquely constructed based on the ptx parameters of type, width, and mult. This allows reuse of ptx among multiple modules.
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2017-04-26 14:33:03 -07:00 |
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single_level_column_mux_array.py
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RELEASE 1.0
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2016-11-08 09:57:35 -08:00 |
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sram.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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tri_gate.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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tri_gate_array.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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utils.py
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Updated gdsMill with new getter routines for router to get by location. Cleaned up vlsiLayout.
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2017-05-17 14:27:14 -07:00 |
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vector.py
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Merge master branch into router
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2017-01-09 14:04:37 -08:00 |
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verilog.py
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RELEASE 1.0
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2016-11-08 09:57:35 -08:00 |
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wire.py
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Removed name option from some modules and autogenerate unique names. Added check to design class to prevent duplicate names by accident. Reduced diff file output verbosity.
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2017-06-02 11:11:57 -07:00 |
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wordline_driver.py
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Improved characterizer.
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2017-07-06 08:42:25 -07:00 |
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write_driver.py
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RELEASE 1.0
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2016-11-08 09:57:35 -08:00 |
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write_driver_array.py
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Removed array_type from ms_flop_array since it is extraneous code.
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2017-07-03 12:08:50 -07:00 |
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