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OpenRAM/compiler
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Matt Guthaus 88740c107f Improve global and code structure using modules. 
Comment and reorganize globals.py
Tests consistently use globals module for OPTions.
Add characterizer as module support.
Modify unit tests to reload new characterizer for ngspice/hspice.
Enable relative and absolute config file arguments so you can run
openram from anywhere on any config file.
 		2017-11-16 13:52:58 -08:00
..
characterizer Improve global and code structure using modules. 2017-11-16 13:52:58 -08:00
gdsMill Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
router Fix unit tests to be DRC clean. 2017-06-07 10:29:53 -07:00
tests Improve global and code structure using modules. 2017-11-16 13:52:58 -08:00
verify Improve global and code structure using modules. 2017-11-16 13:52:58 -08:00
bank.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
bitcell.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
bitcell_array.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
contact.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
control_logic.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
debug.py Improve global and code structure using modules. 2017-11-16 13:52:58 -08:00
delay_chain.py SRAM single bank passing DRC/LVS. 2017-09-13 15:46:41 -07:00
design.py Improve global and code structure using modules. 2017-11-16 13:52:58 -08:00
example_config_freepdk45.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
example_config_scn3me_subm.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
geometry.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
globals.py Improve global and code structure using modules. 2017-11-16 13:52:58 -08:00
hierarchical_decoder.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
hierarchical_predecode.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
hierarchical_predecode2x4.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
hierarchical_predecode3x8.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
hierarchy_layout.py Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
hierarchy_spice.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
lef.py Modify LEF output to have all capital LAYER. Remove extra space before new lines. 2017-08-15 08:21:54 -07:00
ms_flop.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
ms_flop_array.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
nand_2.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
nand_3.py Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
nor_2.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
openram.py Move verify into a module. Make characterizer a module. Move exe searching to modules. 2017-11-15 17:02:53 -08:00
options.py Skeleton code for indirect DRC/LVS/PEX tools. 2017-11-14 14:59:14 -08:00
path.py Added pins to the ptx class. Modified pin class to do lazy write of GDS shapes to allow removal of pins. 2017-10-05 17:35:05 -07:00
pin_layout.py Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
pinv.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
precharge.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
precharge_array.py Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00
ptx.py Fix bug in multifinger ptx. Replace LEF file with new snapped layout. 2017-10-06 16:23:23 -07:00
regress.sh Add regress.sh script for convenience 2016-11-18 08:00:34 -08:00
replica_bitcell.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
replica_bitline.py Two bank SRAMs working in both technologies. 2017-09-29 16:22:13 -07:00
route.py Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays. 2017-08-07 10:24:45 -07:00
sense_amp.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
sense_amp_array.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
single_level_column_mux.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
single_level_column_mux_array.py Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way. 2017-08-24 16:22:14 -07:00
sram.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
tri_gate.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
tri_gate_array.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
utils.py Development version of new pin data structure. Tests pass LVS/DRC except for bank level. 2017-08-23 15:02:15 -07:00
vector.py Merge master branch into router 2017-01-09 14:04:37 -08:00
verilog.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
wire.py Fix new offset snap problems in wordline drive. Fix ptx multifinger pin bug. Add new add_center_rect function. 2017-10-06 15:30:15 -07:00
wordline_driver.py Change default delay modeling to analytical. Add command-line option characterization by simulation (-c). 2017-11-09 11:13:44 -08:00
write_driver.py Add spice pruning for speed-up. Fix spice search bugs. Add time in stages to openram output. 2017-11-14 13:24:14 -08:00
write_driver_array.py Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error. 2017-09-11 14:30:52 -07:00