OpenRAM

characterizer

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

gdsMill

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

router

Fix unit tests to be DRC clean.

2017-06-07 10:29:53 -07:00

tests

Update LEF files with modified blockages.

2017-10-04 20:17:30 -07:00

bank.py

4-bank SRAMs are now working.

2017-10-04 18:05:45 -07:00

bitcell_array.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

bitcell.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

calibre.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

contact.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

control_logic.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

debug.py

Improved characterizer.

2017-07-06 08:42:25 -07:00

delay_chain.py

SRAM single bank passing DRC/LVS.

2017-09-13 15:46:41 -07:00

design.py

Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.

2017-08-07 10:24:45 -07:00

example_config_freepdk45.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

example_config_scn3me_subm.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

geometry.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

globals.py

Improved characterizer.

2017-07-06 08:42:25 -07:00

hierarchical_decoder.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

hierarchical_predecode2x4.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

hierarchical_predecode3x8.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

hierarchical_predecode.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

hierarchy_layout.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

hierarchy_spice.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

lef.py

Modify LEF output to have all capital LAYER. Remove extra space before new lines.

2017-08-15 08:21:54 -07:00

ms_flop_array.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

ms_flop.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

nand_2.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

nand_3.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

nor_2.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

openram.py

Convert print to functional type call like Python 3. Perform error checking that requires Python >2.7 <3.0 for better error checking.

2017-06-12 15:02:48 -07:00

options.py

Enable output filename and path to be in config file. Command line will over-ride config file.

2017-06-12 14:37:15 -07:00

path.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

pin_layout.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

pinv.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

precharge_array.py

Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error.

2017-09-11 14:30:52 -07:00

precharge.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

ptx.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

regress.sh

Add regress.sh script for convenience

2016-11-18 08:00:34 -08:00

replica_bitcell.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

replica_bitline.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

route.py

Fix LEF mismatch due to path/wire hierarchy change. Add characterizer feasible delay/slew check. Update delay tests with new delays.

2017-08-07 10:24:45 -07:00

sense_amp_array.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

sense_amp.py

Two bank SRAMs working in both technologies.

2017-09-29 16:22:13 -07:00

single_level_column_mux_array.py

Fixed several LVS errors. Bank passes LVS for 2-way and 4-way, but not 1-way or 8-way.

2017-08-24 16:22:14 -07:00

single_level_column_mux.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

sram.py

4-bank SRAMs are now working.

2017-10-04 18:05:45 -07:00

tri_gate_array.py

Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error.

2017-09-11 14:30:52 -07:00

tri_gate.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

utils.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

vector.py

Merge master branch into router

2017-01-09 14:04:37 -08:00

verilog.py

RELEASE 1.0

2016-11-08 09:57:35 -08:00

wire.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

wordline_driver.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00

write_driver_array.py

Fix 1-way single bank LVS bug. Full SRAM still not functional. 8-way has DRC error.

2017-09-11 14:30:52 -07:00

write_driver.py

Development version of new pin data structure. Tests pass LVS/DRC except for bank level.

2017-08-23 15:02:15 -07:00