Commit Graph
2715 Commits
Author SHA1 Message Date
Emil J. Tywoniak 9372741e59 select: alias wires don't count for cone depth 2026-09-15 12:00:03 +02:00
Miodrag Milanović f1442ce42e Merge pull request #6182 from YosysHQ/lofty/revert-read_xaiger2
Temporarily revert #6101 and #6077
2026-09-08 04:53:08 +00:00
Lofty 51583d854a Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8"
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
2026-09-07 17:29:08 +01:00
nella c4b6c19580 Rank cells on tuple. 2026-09-04 11:16:24 +02:00
Nick Allison 0bf55a858b Merge pull request #6164 from YosysHQ/nick/fix-6151
Adding error cases to formal backends for invalid formal cells
2026-09-02 14:42:28 +00:00
Miodrag Milanović 28b7a17675 Merge pull request #6115 from YosysHQ/log-sink
log rewrite [sc-748]
2026-09-02 13:03:29 +00:00
nick 3deb8f313e fix 6151 - adding error cases to formal backends / also adding test
cases
2026-09-01 14:34:28 -06:00
nella e0bf46ebc5 Separate non -sat constbits. 2026-08-27 23:10:40 +06:00
nella 7cea58eead More sat constbits tests. 2026-08-27 23:10:40 +06:00
Emil J dd83bbad28 Merge pull request #6116 from antmicro/mgan/hdlname-fix
Fix ignored `hdlname` attribute in `dfflibmap` pass
2026-08-24 11:36:17 +00:00
Emil J e3af33003d Merge pull request #6141 from john-kearney/fix-json-netnames-signed
json: read 'signed' on netnames, matching ports
2026-08-24 10:19:44 +00:00
Emil J 85acd07685 Merge pull request #6123 from sifferman/fix-resetall-default-nettype
Fix resetall not affecting default_nettype
2026-08-24 09:47:04 +00:00
Daniel M'BOUYOU 25c7053114 arith_tree: add regression tests for truncating narrow chain links
#6130 fixed arith_tree so that a chain link narrower than its consumer
is left out of the tree, and added an equivalence regression for the
exact failing shape. Cover what that test does not: structural checks
that the narrow link survives as its own cell, on both the raw $add
path and the alumacc $alu path, and a mixed case where a wider chain
consuming the truncated link as a leaf still folds and stays
equivalent.

Signed-off-by: Daniel M'BOUYOU <[email protected]>
2026-08-21 10:38:58 +02:00
John Kearney 0f5efca3c9 json: read 'signed' attribute on netnames, matching ports
The JSON backend writes "signed": 1 for any signed wire, including
internal nets. The frontend only parsed the attribute for ports,
so a write-read roundtrip silently cleared is_signed on internal
nets. Signed internal wires became unsigned between the two passes.

Fix: parse 'signed' in the netnames loop, next to the existing
upto/offset handling. Regression test does a full roundtrip and
checks the internal signed wire survives.
2026-08-20 22:20:24 -07:00
Nick Allison 5c0100c45e Merge branch 'main' into check-cells-backends 2026-08-20 13:07:22 -06:00
Lofty 4ad3dc46ad Merge pull request #6137 from YosysHQ/lofty/abc-refactor-14
synth_gatemate: remove classic ABC mapping for LUTs
2026-08-20 10:33:07 +00:00
Zane Hambly bec454465f Merge branch 'main' into check-cells-backends 2026-08-20 21:42:56 +12:00
nella 59a3826bbd Merge pull request #6130 from DanielMBouyou/arith-tree-narrow-link
arith_tree: do not flatten a chain link narrower than its consumer
2026-08-20 08:40:25 +00:00
Lofty 030e13569c synth_gatemate: remove classic ABC mapping for LUTs 2026-08-20 09:33:47 +01:00
Miodrag Milanovic 2e113f5eff log: create LogManager singleton and move implementation 2026-08-19 15:59:46 +02:00
Lofty ee75cd3ea0 synth_lattice: remove classic ABC mapping 2026-08-19 11:43:00 +01:00
Lofty 737560c471 synth_fabulous: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 5fe16f60f9 synth_efinix: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 6df15312cc synth_anlogic: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 086cd8e685 synth_xilinx: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Lofty 44bab117d7 synth_ice40: remove classic ABC mapping 2026-08-19 11:42:59 +01:00
Daniel M Bouyou e5c56c6400 arith_tree: do not flatten a chain link narrower than its consumer
sole_chainable_consumer folded a cell into its consumer without ever
comparing widths. A link truncates its result at its own Y width, and that
truncation is invisible only when the consumer truncates at least as hard,
since (x % 2**link) % 2**parent == x % 2**parent holds only when
parent <= link. When the consumer is wider, the carry the link discards
becomes observable, and flattening the chain silently recovers it.

For

  module top(input [7:0] a, b, c, output [8:0] o);
    wire [7:0] t = a + b;
    assign o = t + c;
  endmodule

synth -arith_tree computes a + b + c where the design specifies
((a + b) % 256) + c. The two differ by 256 whenever a + b overflows,
for example at a=169 b=135 c=7.

alumacc already guards the structurally identical $macc merge using
macc_may_overflow(); arith_tree carried no equivalent check.

Add two cases to tests/arith_tree/arith_tree_equiv.ys: equiv_double_neg
widened to a 5 bit result, and a dedicated equiv_narrow_intermediate.
2026-08-18 12:06:48 +02:00
nella 598862f45b Merge pull request #6125 from YosysHQ/nella/share-sat-effort
share: limit SAT effort [sc-750]
2026-08-17 12:18:28 +00:00
nella 027677d43b Move scl cache args to libcache, fix -disable. 2026-08-17 12:37:49 +02:00
nella bbcbdcec09 Add test. 2026-08-17 12:20:51 +02:00
nella 5efa8187ad Add control over scl cache. 2026-08-17 10:49:45 +02:00
Ethan Sifferman 4bd6be5b0f reset default_nettype on `resetall for the lexer 2026-08-16 14:26:21 -07:00
Nick Allison f77ddfb875 Merge pull request #6114 from YosysHQ/nick/fix-6085
cmp2lut techmap fix + re-adding tests
2026-08-14 19:57:43 +00:00
nick b57ffad7d0 Adding test to demonstrate techmap failure with lut_cmp 2026-08-14 10:08:40 -06:00
Miodrag Milanovic cbbd8c0dfd log: convert all to sinks 2026-08-14 11:55:46 +02:00
Mateusz Gancarz 1c1c56dfad dfflibmap: move all attributes to new cells 2026-08-13 15:56:43 +02:00
ZaneHam b7b8ea9784 smt2, btor: error on $check cells instead of dropping them
Both backends only looked for $assert/$assume/$cover, so a $check cell was
never visited and the resulting formal output carried no proof obligations at
all. write_smv already errors via its catch-all; this follows its message.
2026-08-14 00:15:34 +12:00
nella b8959e70ba Merge pull request #6072 from YosysHQ/nella/dlatchlibmap-cleanup
Update to `dfflibmap` to be able to map LATCHes (clean up of #5976)
2026-08-13 08:38:19 +00:00
Miodrag Milanovic 14afc00862 log: Refactor code a bit more 2026-08-13 09:22:01 +02:00
Sean Luchen 8d6be2467b Add LogSink & LogMessage classes for a more robust sink solution.
Signed-off-by: Sean Luchen <[email protected]>
2026-08-13 09:01:15 +02:00
nella 7f5b7aacb9 Count module output ports as consumers. 2026-08-12 10:00:30 +02:00
nella b19d906075 Fix replace_known misindexing on constant S bits. 2026-08-11 07:07:33 +02:00
Lofty fd6367405e Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8
abc_ops_reintegrate: xaiger2 compatibility
2026-08-10 13:14:40 +00:00
Loftyandnella d1357f171f fix handling of multiple modules
Co-authored-by: nella <[email protected]>
2026-08-10 10:17:31 +01:00
nellaandIztok Jeras 9050446798 Add latch tests, extend dff tests.
Co-authored-by: Iztok Jeras <[email protected]>
2026-08-10 10:59:03 +02:00
nellaandIztok Jeras 011c3fc8c3 Add latch mapping.
Co-authored-by: Iztok Jeras <[email protected]>
2026-08-10 10:59:03 +02:00
nella 9c144d59aa Fix OOB read. 2026-08-07 14:29:14 +02:00
nella 7bbb69872c Add regression tests. 2026-08-06 09:14:44 +02:00
Emil J 72ce1b63d7 Merge pull request #6090 from YosysHQ/emil/hierarchy-fix-keep-cache-again
hierarchy: fix keep cache usage by caching false too 2
2026-08-05 21:54:55 +00:00
Emil J. Tywoniak 253388a87f hierarchy: fix cache usage by caching false too 2 2026-08-05 23:32:37 +02:00