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2142 Commits
Author SHA1 Message Date
Miodrag Milanovic a80623137a sv-elab: Update to release 2026-09-08 2026-09-08 11:58:13 +02:00
Lofty 51583d854a Revert "Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8" 
This reverts commit fd6367405e, reversing
changes made to 0f2bcb94b7.
 2026-09-07 17:29:08 +01:00
Lofty c53d452134 Revert "Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10" 
This reverts commit 621d943ac8, reversing
changes made to 598862f45b.
 2026-09-04 11:16:11 +01:00
Miodrag Milanović 28b7a17675 Merge pull request #6115 from YosysHQ/log-sink 
log rewrite [sc-748]
 2026-09-02 13:03:29 +00:00
Miodrag Milanovic 7c10ee1c58 Update sv-elab as of 2026-09-01 2026-09-01 08:20:05 +02:00
Miodrag Milanovic 726aff678f log: remove log_ prefix and unified some namings 2026-08-31 11:20:21 +02:00
Emil J e3af33003d Merge pull request #6141 from john-kearney/fix-json-netnames-signed 
json: read 'signed' on netnames, matching ports
 2026-08-24 10:19:44 +00:00
Emil J 85acd07685 Merge pull request #6123 from sifferman/fix-resetall-default-nettype 
Fix resetall not affecting default_nettype
 2026-08-24 09:47:04 +00:00
tangxifan 02dc5a82d7 [core] add a cmake option to disable unit test during compilation; Use cmake_current_source for submodule integration 
[core] debug yosys version extraction

[core] debug

[core] now cache the cmake source dir

[core] debug

[core] debug kernel dependencies

[core] debug common include directories

[core] debug

[core] debug simlib_help.inc

[core] debug pmgen py path in cmake

[core] syntax

[core] debug flex source

[core] restore

[core] debug executable output as it now shows linking to .

[core] debug yosys-abc directory

[core] debug cmake share directory

[core] debug yosys abc

[core] restore shared directory location as yosys requires fixed location

[core] rework link target to yosys sub dir under build

[core] fixed the bug on yosys-config.install location for install

[core] cmake syntax

[core] correct the location for share directory

[core] debug

[core] debug

[core] debug

[core] enforce internal attributes; rename the YOSYS_ENABLE_UNIT_TESTS; use YOSYS_CMAKE_BINARY_DIR for all

[core] apply review comments

[core] rename

[core] change all the CMAKE_BINARY_DIR to YOSYS_CMAKE_BINARY_DIR

[core] replace CMAKE_SOURCE_DIR to YOSYS_CMAKE_SOURCE_DIR
 2026-08-21 12:09:04 -07:00
John Kearney 0f5efca3c9 json: read 'signed' attribute on netnames, matching ports 
The JSON backend writes "signed": 1 for any signed wire, including
internal nets. The frontend only parsed the attribute for ports,
so a write-read roundtrip silently cleared is_signed on internal
nets. Signed internal wires became unsigned between the two passes.

Fix: parse 'signed' in the netnames loop, next to the existing
upto/offset handling. Regression test does a full roundtrip and
checks the internal signed wire survives.
 2026-08-20 22:20:24 -07:00
Miodrag Milanovic caad7779e0 log: propagate format information 2026-08-20 17:30:44 +02:00
Miodrag Milanovic 2e113f5eff log: create LogManager singleton and move implementation 2026-08-19 15:59:46 +02:00
Lofty 621d943ac8 Merge pull request #6101 from YosysHQ/lofty/abc-refactor-10 
read_xaiger2: remove
 2026-08-17 17:42:25 +00:00
Ethan Sifferman 4bd6be5b0f reset default_nettype on `resetall for the lexer 2026-08-16 14:26:21 -07:00
Miodrag Milanovic cbbd8c0dfd log: convert all to sinks 2026-08-14 11:55:46 +02:00
nella b8959e70ba Merge pull request #6072 from YosysHQ/nella/dlatchlibmap-cleanup 
Update to `dfflibmap` to be able to map LATCHes (clean up of #5976)
 2026-08-13 08:38:19 +00:00
Miodrag Milanovic dc6ac344b7 Update slang and sv-elab to latest 2026-08-12 13:13:30 +02:00
Lofty 1dce7895e0 read_xaiger2: remove 2026-08-11 08:56:55 +01:00
Lofty fd6367405e Merge pull request #6077 from YosysHQ/lofty/abc-refactor-8 
abc_ops_reintegrate: xaiger2 compatibility
 2026-08-10 13:14:40 +00:00
Loftyandnella d1357f171f fix handling of multiple modules 
Co-authored-by: nella <[email protected]>
 2026-08-10 10:17:31 +01:00
nella a03e5ec2ca Style fixups. 2026-08-10 10:59:03 +02:00
nellaandIztok Jeras 011c3fc8c3 Add latch mapping. 
Co-authored-by: Iztok Jeras <[email protected]>
 2026-08-10 10:59:03 +02:00
Miodrag Milanovic 92bdbafe82 verific: Added sv2023 support, and cleanup 2026-08-07 08:41:55 +02:00
Catherine 1277640bdf CMake: add missing dependency edges for synth_* passes. 2026-08-06 14:48:56 +00:00
Lofty 6d9f5d1b0c wip 2026-08-03 12:34:01 +01:00
nella 250a467518 Attr file:line. 2026-07-31 10:31:44 +02:00
nella 2b5755178f Clean up diagnostics. 2026-07-31 10:31:44 +02:00
Emil J. Tywoniak dfa887637a const2ast: handle constant parsing from the command-line again 2026-07-31 10:31:44 +02:00
Emil J. Tywoniak 5f5f8b99b1 liberty: cleanup 2026-07-30 16:44:12 +02:00
Emil J. Tywoniak ef69127001 liberty: refactor out constant bools 2026-07-28 16:39:08 +02:00
Emil J. Tywoniak db2b3a22e9 liberty: remove optimization to simplify control flow, fixing polarities in set&reset behavior modeling 2026-07-27 22:09:57 +02:00
Miodrag Milanovic eb3a15cd8c Update sv-elab to 3dddccd 2026-07-15 08:24:46 +02:00
Miodrag Milanovic 30ba4328e7 Use system libs when available 2026-07-13 15:26:00 +02:00
Michael Baier 8f0028652a long long to int truncation checks 2026-07-10 14:36:39 +02:00
Michael Baier eb4e29810e Fixed Overflow error in checking width 2026-07-09 14:34:56 +02:00
Michael Baier 42092cbc77 Adding width checks to frontend 2026-07-09 14:34:56 +02:00
Lofty 75286287c6 Merge pull request #5973 from YosysHQ/lofty/abc-refactor-7 
Move rename logic to abc_ops_reintegrate
 2026-07-09 08:46:46 +00:00
Martin Povišer ff8a867764 Bump sv-elab to 2026-07-07 2026-07-07 15:20:19 +02:00
Miodrag Milanovic 05c0adae77 Slang frontend integration 2026-07-06 15:49:56 +02:00
Miodrag Milanovic a689342207 Remove trailing whitespaces 2026-06-23 07:24:59 +02:00
Miodrag Milanovic 48a3dcc02a End of file fix 2026-06-23 07:23:41 +02:00
Lofty 091d2a7814 Move rename logic to abc_ops_reintegrate 2026-06-19 10:46:47 +01:00
nella 5d7486115a Merge pull request #5887 from YosysHQ/nella/fix-signedness-4402 
Fix: `read_verilog` doesn't respect `signed` keyword
 2026-06-18 16:53:37 +00:00
Krystine Sherwin b79c7c008d simplify.cc: Fix crash when identifier matches module 
Also update one of the AST debug prints that is guarded by an `#if 0` but was out of date.
 2026-06-12 11:54:53 +12:00
Lofty 73c217133b Merge pull request #5934 from YosysHQ/lofty/abc9-refactor-5 
read_aiger: import standard-cell mappings from ABC
 2026-06-08 09:38:34 +00:00
Lofty 2a4525efbb read_aiger: import standard-cell mappings from ABC 2026-06-05 11:02:58 +01:00
Miodrag Milanovic 102f008194 Remove EMSCRIPTEN leftovers 2026-06-05 10:03:27 +02:00
Miodrag Milanovic 5f2456ac03 WASI now support filesystem 2026-06-05 09:18:00 +02:00
Miodrag Milanović 693d5a7eb0 Merge pull request #5903 from YosysHQ/krys/verific_memsize 
verific: Fix non-contiguous memory flattening producing out of bounds accesses in some cases
 2026-06-04 05:43:04 +00:00
Miodrag MilanovicandCatherine ce280354cf Update CI scripts for CMake 
Co-authored-by: Catherine <[email protected]>
 2026-06-03 08:58:11 +00:00