luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
17,909 Commits 146 Branches 67 Tags 50 MiB
Commit Graph

17909 Commits

Author SHA1 Message Date
Akash Levy dd08ba75bc
Merge pull request #100 from Silimate/negopt-pass-pr 
Add negopt pass with comprehensive pattern matching
 2026-02-04 01:44:45 -08:00
Akash Levy 3bffeee622
Merge pull request #99 from Silimate/sim 
Activity annotation will use timescale from VCD
 2026-02-04 01:26:25 -08:00
Akash Levy 715e062bcd Merge branch 'main' into negopt-pass-pr 2026-02-04 00:15:53 -08:00
Akash Levy 33bcfe26dd Merge branch 'main' into sim 2026-02-03 23:57:24 -08:00
Akash Levy 807df40422 Undo the weird abc changes 2026-02-03 23:21:48 -08:00
tondapusili 643427d9c9 Add negopt pass with comprehensive pattern matching 
This commit introduces the negopt pass with pre/post optimization modes
for handling negation patterns in arithmetic circuits.

Pre-optimization patterns (expose for tree balancing):
- manual2sub: (a + ~b) + 1 → a - b
- sub2neg: a - b → a + (-b)
- negexpand: -(a + b) → (-a) + (-b) [with output width fix]
- negneg: -(-a) → a
- negmux: -(s ? a : b) → s ? (-a) : (-b)

Post-optimization patterns (cleanup/rebuild):
- negrebuild: (-a) + (-b) → -(a + b)
- muxneg: s ? (-a) : (-b) → -(s ? a : b)
- neg2sub: a + (-b) → a - b

All patterns use nusers() for fanout checking (standard Yosys style).
Comprehensive test coverage with positive/negative cases and formal
verification via equiv_opt.
 2026-02-03 17:21:21 -08:00
Stan Lee bea2a7d473 add few debug 2026-02-03 14:40:33 -08:00
Stan Lee ce959ec1bb fixes 2026-02-03 12:42:33 -08:00
Stan Lee 6620d098d4 lower verbosity 2026-02-03 12:05:14 -08:00
Akash Levy 8e5d24aa6b Bump yosys to latest 2026-02-03 06:08:36 -08:00
Miodrag Milanović 6dbe03f0f5
Merge pull request #5667 from Logikable/vhdl 
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
 2026-02-03 07:59:52 +01:00
github-actions[bot] 153ddc0c84 Bump version 2026-02-03 00:33:37 +00:00
Sean Luchen 224549fb88 Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. 
Signed-off-by: Sean Luchen <seanluchen@google.com>
 2026-02-02 15:26:03 -08:00
KrystalDelusion 414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal 
Handle ABC nonfatal "Error:" messages
 2026-02-03 08:55:05 +13:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
Miodrag Milanović f5c8368f7a
Merge pull request #5662 from YosysHQ/update_abc 
Update ABC as per 2026-02-02
 2026-02-02 13:44:56 +01:00
Miodrag Milanovic b88d6588bc Update ABC as per 2026-02-02 2026-02-02 11:25:57 +01:00
Akash Levy 7c70026610 Fix verific issue 2026-02-01 00:16:10 -08:00
Akash Levy bdc9ad9f53 Bump version 2026-01-30 19:29:00 -08:00
Miodrag Milanović ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd 
Add unistd header for Linux
 2026-01-30 08:17:43 +01:00
Miodrag Milanović 382b28acbe
Merge pull request #5648 from YosysHQ/verific_moreopts 
verific: fixed -sv2017 option and added ability to set VHDL standard
 2026-01-30 08:17:19 +01:00
Akash Levy 892ef37b26 Undo 2026-01-29 19:36:36 -08:00
Akash Levy bbdf5042c7 Add PYTHON_INCLUDE_FLAGS 2026-01-29 19:20:46 -08:00
Robert O'Callahan 9c56c93632 Add missing newlines to some 'log_error's 2026-01-30 01:52:19 +00:00
Robert O'Callahan 6af1b5b19c Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal 2026-01-30 01:52:19 +00:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
github-actions[bot] 106f289e31 Bump version 2026-01-30 00:30:58 +00:00
KrystalDelusion 5a4ad6a6d0
Merge pull request #5640 from YosysHQ/krys/fix_mod.py 
Don't use `module mod_name(...)` style in cell libs
 2026-01-30 11:40:07 +13:00
Emil J a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal 
Dump module details when `design_equal` fails
 2026-01-29 18:57:24 +01:00
Natalia 61b1c3c75a use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
Natalia 7439d2489e add assertion to run_pass test 2026-01-29 02:23:07 -08:00
Miodrag Milanovic b70f527c67 verific: fixed -sv2017 option and added ability to set VHDL standard if applicable 2026-01-29 10:32:30 +01:00
Miodrag Milanović 6ba8f3dc19
Merge pull request #5647 from YosysHQ/update_abc 
ABC update (MINGW fix)
 2026-01-29 10:12:25 +01:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Miodrag Milanovic 6007b68e9c ABC update (MINGW fix) 2026-01-29 09:30:12 +01:00
Natalia 8d504ecb48 verific: use MFCU for SV file list 2026-01-29 00:03:28 -08:00
Akash Levy 1dd846022b Fix opt_dff cell naming 2026-01-28 23:36:49 -08:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
Akash Levy 9f911e3d63 Reorder ff.remove in opt_dff 2026-01-28 20:58:01 -08:00
Akash Levy 5993d2fec8 Remove annoying test case 2026-01-28 19:18:06 -08:00
Akash Levy bb2aadb9ef Merge remote-tracking branch 'upstream/main' 2026-01-28 19:09:56 -08:00
Akash Levy 4e937450b4
Merge pull request #97 from Silimate/reg-rename 
Bug fix for reg_rename pass
 2026-01-28 19:08:26 -08:00
Akash Levy 16087ae931 Merge from upstream 2026-01-28 18:17:50 -08:00
Stan Lee c0a1529eb8 reduce verbosity 2026-01-28 18:05:21 -08:00
Akash Levy e8d27892f0
Merge pull request #96 from Silimate/fanoutbuf_src_attr 
Changed fanoutbuf.cc to include src attributes on buffers connected t…
 2026-01-28 17:50:46 -08:00
Stan Lee 04faedd131 syntax err 2026-01-28 17:40:57 -08:00
Stan Lee dfef18010d shorter lines 2026-01-28 17:20:19 -08:00
Stan Lee 932c4452b5 better working implementation 2026-01-28 17:00:46 -08:00
github-actions[bot] 1f6a13dac7 Bump version 2026-01-29 00:31:03 +00:00
AdvaySingh1 3ce57442de Changed fanoutbuf.cc to include src attributes on buffers connected to input and output wires 2026-01-28 15:33:13 -08:00