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18,002 Commits 132 Branches 68 Tags 53 MiB
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21 Commits

Author SHA1 Message Date
AdvaySingh1 499e83a549 Switched to using CE module. Mostly retaining SAT gates. Still needs speedup 2026-02-17 12:41:59 -08:00
AdvaySingh1 e755f6c42e Added initial simulation. Incorrect simulation -- changed the number of accedpted results as well as increasing runtime 2026-02-17 12:14:53 -08:00
AdvaySingh1 2212d85626 Changed configurations to match the OpenROAD project 2026-02-17 11:57:56 -08:00
AdvaySingh1 144db54c4e Changed to inverse hashing for more flexibility 2026-02-17 11:53:06 -08:00
AdvaySingh1 f0de3ae8de Initial sat_clockgate pass pre speed optimization 2026-02-17 11:19:18 -08:00
AdvaySingh1 cc6605f8e2 Added passing on the args into the clockgate pass so there's an icg cell for the mapping 2026-02-17 10:49:18 -08:00
AdvaySingh1 2ab34262ec Added profiling info before and after sat_clockgate pass 2026-02-17 09:23:32 -08:00
AdvaySingh1 3567960671 Changed hashing from string to pair with vector and bool 2026-02-13 17:01:58 -08:00
AdvaySingh1 5ce8aada27 Added profiling for literal count 2026-02-13 16:34:15 -08:00
AdvaySingh1 3442bc3a85 Changed indexing to be based on the literal ID in EZSat and sorted to allow better hashing 2026-02-13 16:15:31 -08:00
AdvaySingh1 80fbdf7e6a Removed duplication of vectors and called clockgate pass post creating enable signals 2026-02-13 15:33:45 -08:00
AdvaySingh1 feffbbe32c Added initial impl based on OpenROAD 2026-02-12 16:12:50 -08:00
AdvaySingh1 514c01efd2 Added prune expressions list TODO 2026-02-12 12:14:25 -08:00
AdvaySingh1 745f17a34e Changed input_set_is_enable_exact to XOR Mitter 2026-02-12 11:10:10 -08:00
AdvaySingh1 532d1d45a8 Resolved adding SigBits from Q using static EXCLUDE_Q_FROM_ENABLE knob 2026-02-11 15:08:49 -08:00
AdvaySingh1 4ca4392e9b Simplied recursion in sat_clockgate pass 2026-02-11 14:56:46 -08:00
AdvaySingh1 dd3f2e370c Fixed naming for bfs_find_potential_enable_inputs 2026-02-11 12:31:13 -08:00
AdvaySingh1 5b384511f2 Added initial SatClockgateWorker 2026-02-11 11:02:15 -08:00
AdvaySingh1 b4cd82bacf Added initial printing of the clocks with dump_flipflops_to_file 2026-02-11 10:56:07 -08:00
AdvaySingh1 6ad01fa850 Added initial pass structure 2026-02-10 14:33:37 -08:00
AdvaySingh1 b4ef420c3f Added inital SAT based clock gating file 2026-02-10 14:02:15 -08:00