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2142 Commits

Author SHA1 Message Date
Emil J b2816b22c5
Merge pull request #4965 from YosysHQ/krys/gen_err_files 
More *.err files in test failures
 2025-03-28 13:08:44 +01:00
Emil J ec8b745929
Merge pull request #4733 from antmicro/fix-setundef-pass-for-params 
Fix setting bits of parameters in setundef pass
 2025-03-28 13:06:04 +01:00
Akash Levy 7bbd7ef3eb
Merge pull request #75 from williamzhu17/test-yosys-fix 
Fixes for the test-yosys
 2025-03-27 17:23:49 -07:00
williamzhu17 7208e05bdf fixes for the yosys test 2025-03-27 17:19:08 -07:00
williamzhu17 770eecb4f7 code cleanup 2025-03-27 15:27:15 -07:00
William Zhu eefdcbfe81 added ornot tests 2025-03-27 15:23:18 -07:00
William Zhu 7f04cc6755 removed dump verilog 2025-03-27 15:14:28 -07:00
William Zhu 8666e9ae45 tests for mux_andnot 2025-03-27 15:13:57 -07:00
William Zhu d493a55025 forgot to add some things to previous commit 2025-03-27 12:40:41 -07:00
William Zhu 3b8330c44f reverted some extra unneccessary checks 2025-03-27 12:40:21 -07:00
William Zhu a03553b54e added some extra comments and checks 2025-03-27 12:36:15 -07:00
William Zhu cc4c9c4eba first tests for opt_expand 2025-03-27 12:31:37 -07:00
Akash Levy 3d13f7aae2 Bump to latest 2025-03-26 14:56:10 -07:00
KrystalDelusion 5b6b3d01bf
Update gen-tests-makefile.sh 
Keep file extensions so that e.g. tribuf.ys and tribuf.sh don't try to output to the same log file.
 2025-03-27 10:33:51 +13:00
KrystalDelusion 8a68ae6023
Update gen-tests-makefile.sh 2025-03-27 10:10:49 +13:00
Anhijkt cb03a1ec21 ice40_dsp: fix test 2025-03-26 15:13:05 +02:00
Scott Ashcroft 518986d45c Make cxxrtl tests work on 32-bit by using __builtin_clzll when needed 2025-03-25 13:12:04 +00:00
KrystalDelusion a647731812
Merge pull request #4677 from YosysHQ/emil/opt_merge-hashing 
opt_merge: hashing performance and correctness
 2025-03-25 10:36:02 +13:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
Emil J. Tywoniak 980a0a15c1 stat: allow gzipped liberty files 2025-03-19 13:43:44 +01:00
Anhijkt 5ae32efca5 ice40_dsp: add test 2025-03-15 20:05:57 +02:00
Akash Levy 1c0d4a43b3
Merge branch 'YosysHQ:main' into main 2025-03-14 18:07:55 -07:00
KrystalDelusion 9f1271bee0
Merge pull request #4922 from Anhijkt/fix-splitcells-assert 
splitcells: Fix the assertion bug caused by out-of-bound offset
 2025-03-14 16:52:38 +13:00
Krystine Sherwin 8405b3b723
select: Fix -none and -clear 
If the selection stack only has one element (which it normally does), then
`design->pop_selection()` automatically resets to the default full selection.
This is a problem for `select [-none | -clear]` which were trying to replace the
current selection, but because the pop added an extra element when the `execute`
returned, the extra selection (the one we actually wanted) gets popped too. So
instead, reassign `design->selection()` in the same way as if we called `select
[selection]`.

Also adds selection stack tests, and removes the accidentally-committed
`boxes_dummy.ys`.
 2025-03-14 16:32:18 +13:00
Krystine Sherwin 9a9cd05f6c
tests: Fixes for boxes 
cxxrtl `test_unconnected_output` and simple_abc9 `abc9.v` both expect boxed modules in the outputs, so make sure they work as expected.
 2025-03-14 14:08:15 +13:00
Krystine Sherwin 061c234559
tests/select: Add tests for selections with boxes 2025-03-14 14:05:40 +13:00
Alain Dargelas 68312d046a Fix Yosys test failures 2025-03-13 14:15:13 -07:00
Akash Levy 6f818af110 Ignore test collateral 2025-03-13 01:55:22 -07:00
Akash Levy 0a68eb32b3 Disable sub-neg peepopt 2025-03-13 01:55:14 -07:00
Akash Levy e4066b784d Merge remote-tracking branch 'upstream/main' 2025-03-12 19:21:32 -07:00
Martin Povišer 6da543a61a
Merge pull request #4818 from povik/macc_v2 
Add `$macc_v2`
 2025-03-12 22:55:40 +01:00
Akash Levy 4d4e574ebb
Merge pull request #60 from alaindargelas/peepopt_neg_sub 
neg-sub peepopt pass
 2025-03-10 15:48:49 -07:00
Alain Dargelas e1671b45b6 Code review 2025-03-10 14:44:14 -07:00
Akash Levy e360511339
Merge branch 'YosysHQ:main' into main 2025-03-10 14:21:49 -07:00
Alain Dargelas 6de80bc6b3 neg sub pass 2025-03-10 13:47:06 -07:00
Anhijkt be3dfdc5ad splitcells: add tests 2025-03-10 19:41:22 +02:00
Martin Povišer d8a4991289
Merge pull request #4931 from povik/buf-clean 
opt_clean, simplemap: Add `$buf` handling
 2025-03-10 15:10:17 +01:00
Emil J. Tywoniak 33bfc9d19c opt_merge: test more kinds of cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak ae7a97cc2d opt_merge: test some unary cells 2025-03-10 13:14:06 +01:00
Emil J. Tywoniak 176faae7c9 opt_merge: fix trivial binary regression 2025-03-10 13:14:06 +01:00
Martin Povišer 557047fe1e opt_clean, simplemap: Add `$buf` handling 2025-03-07 16:08:38 +01:00
Akash Levy fa97c4830e Generalize muxadd to muxorder 2025-03-06 16:57:47 -08:00
Akash Levy 881080a827 Merge upstream 2025-03-05 07:54:26 -08:00
N. Engelhardt 268a034b21
Merge pull request #4866 from YosysHQ/ql_ioff 
add IOFF inference for qlf_k6n10f
 2025-03-03 14:12:09 +00:00
Akash Levy 9d3b7f7474
Merge branch 'YosysHQ:main' into main 2025-02-26 09:51:44 -08:00
Emil J b4a169527d
Merge pull request #4894 from YosysHQ/emil/abstract 
Add `abstract` pass for formal verification
 2025-02-25 11:16:37 +01:00
Emil J. Tywoniak 3f60a2cc67 abstract: test -slice from:to for -init 2025-02-25 00:22:14 +01:00
Emil J. Tywoniak 3cb7054e53 abstract: test -slice for all modes, -rtlilslice for -init 2025-02-25 00:18:16 +01:00
Emil J. Tywoniak 5bd18613bb abstract: test -init 2025-02-19 23:03:43 +01:00
Alain Dargelas 929c817384 splitnets new options 2025-02-19 09:43:53 -08:00
Emil J. Tywoniak 34e3fcbb31 abstract: test -value 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak d3a90021ad abstract: test -state 2025-02-18 17:08:45 +01:00
Jannis Harder 7cd822b7f5 rtlil: Add {from,to}_hdl_index methods to Wire 
In the past we had the occasional bug due to some place not handling all
4 combinations of upto/downto and zero/nonzero start_offset correctly.
 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak 387d0de383 abstract: -state allow partial abstraction, don't use buffer-normalized mode 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak 6027030215 abstract: -value MVP, use buffer-normalized mode 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak 4637fa74e3 abstract: -init MVP 2025-02-18 17:08:45 +01:00
Emil J. Tywoniak e4ca7b8846 abstract: -state MVP 2025-02-18 17:08:45 +01:00
Akash Levy 33c72b0f25
Merge branch 'YosysHQ:main' into main 2025-02-15 15:54:28 -08:00
Akash Levy c4254a9a95 Final cleanup 2025-02-14 10:18:13 -08:00
Akash Levy 1b13b5d6ea Move segv and reenable loops.v test 2025-02-14 10:02:30 -08:00
Akash Levy fd811ddaee Cleanup 2025-02-14 08:48:27 -08:00
Akash Levy 9cc82c7044 Revert clocking.ys 2025-02-13 20:32:17 -08:00
Akash Levy c8c97ea00b Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
Krystine Sherwin db5b76edc1
Add test for shifting by INT_MAX 
Currently resulting in CI failing on main during fsm checks which generate a circuit that simplifies to this.
 2025-02-14 14:01:27 +13:00
Akash Levy 4e45a86e12
Merge branch 'YosysHQ:main' into main 2025-02-06 12:29:43 -08:00
N. Engelhardt 303a386ecc create duplicate IOFFs if multiple output ports are connected to the same register 2025-01-31 11:28:57 +01:00
Jannis Harder 40c690b030 extract_fa: Add test case 2025-01-30 18:45:06 +01:00
N. Engelhardt 9da4fe747e fix bus ioff inference 2025-01-28 11:23:36 +01:00
Martin Povišer 916fe998ab macc_v2: Add test 2025-01-27 13:19:26 +01:00
N. Engelhardt 2241a65f78 fix tests not expecting ioffs 2025-01-24 21:29:10 +01:00
N. Engelhardt 1cf8e7c7db add ioff inference for qlf_k6n10f 2025-01-24 21:17:15 +01:00
Martin Povišer c5fd96ebb0 macc_v2: Start new cell 2025-01-24 12:38:03 +01:00
Akash Levy 2ae7490adf Disable Verific blackbox checks (different from our preferred approach) 2025-01-21 05:46:40 -08:00
Akash Levy bca65ceff7 opt_clean was removing the unused bits annotation 2025-01-16 19:48:31 -08:00
Akash Levy ab338b33cb Use equiv_opt -nocells to ensure everything is ok since dffs retain their name 2025-01-16 19:40:18 -08:00
Akash Levy 67a93dc76d scopeinfo inverted 2025-01-16 19:36:42 -08:00
Akash Levy 90f980eb66 Changed boolopt naming 2025-01-16 19:36:27 -08:00
Akash Levy 53ed83fcac Rename verific to import in tests and update README explanation 2025-01-16 19:34:02 -08:00
Alain Dargelas 84c6be1edd Add splitfanout tests 2025-01-16 12:04:53 -08:00
Alain Dargelas 31a5197a1c muxadd and muldiv_c peepopt 2025-01-15 16:57:19 -08:00
Akash Levy 5c514e00a4 Sync with upstream 2025-01-13 17:20:59 -08:00
N. Engelhardt 7e3990b681
Merge pull request #4837 from YosysHQ/json_scopinfo_opt 
write_json: add option to include $scopeinfo cells
 2025-01-10 09:57:22 +00:00
N. Engelhardt 77b28442a5 emit $scopeinfo cells by default 2025-01-08 14:47:46 +01:00
Martin Povišer ca0ace66bc
Merge pull request #4817 from povik/macc_v2-1 
macc: Stop using the B port
 2025-01-08 14:42:51 +01:00
N. Engelhardt dab7905cbe write_json: add option to include $scopeinfo cells 2025-01-08 13:33:56 +01:00
Martin Povišer 652a1b9806 macc: Stop using the B port 
The B port is for single-bit summands. These can just as well be
represented as an additional summand on the A port (which supports
summands of arbitrary width). An upcoming `$macc_v2` cell won't be
special-casing single-bit summands in any way.

In preparation, make the following changes:

 * remove the `bit_ports` field from the `Macc` helper (instead add any
   single-bit summands to `ports` next to other summands)

 * leave `B` empty on cells emitted from `Macc::to_cell`
 2025-01-08 13:03:35 +01:00
Akash Levy 443613da69
Merge branch 'YosysHQ:main' into main 2025-01-07 00:56:19 -05:00
Martin Povišer 41e4aa8f0a
Merge pull request #4819 from povik/wreduce-resign 
wreduce: Optimize signedness when possible
 2025-01-06 15:27:55 +01:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J 6ab5be4a0e
Merge pull request #4814 from YosysHQ/emil/make-test-fasterer 
test: every test everywhere all at once
 2024-12-18 19:02:39 +01:00
Martin Povišer 08778917db wreduce: Optimize signedness when possible 2024-12-16 12:57:08 +01:00
Emil J. Tywoniak 6240aec433 test: restore verific handling, nicer naming 2024-12-13 10:24:47 +01:00
Akash Levy 1242db626f Merge remote-tracking branch 'upstream/main' 2024-12-12 22:49:19 -08:00
N. Engelhardt 378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
Emil J. Tywoniak 603e5eb30a test: every test everywhere all at once 2024-12-12 01:28:36 +01:00
Akash Levy caaef5ac14
Merge branch 'YosysHQ:main' into main 2024-12-11 12:00:34 -08:00
N. Engelhardt 03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Martin Povišer 4bd6061709
Merge pull request #4799 from povik/wrapcell-unused 
wrapcell: Optionally track unused outputs
 2024-12-10 21:16:28 +01:00
Emil J. Tywoniak 55dcf0e200 tests: fix dfflibmap test - false negative conflict multiple -liberty vs enable inference 2024-12-10 15:48:23 +01:00
Martin Povišer 48c8d70a45 wrapcell: Test `check -assert` post wrapping 2024-12-10 15:13:31 +01:00