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4964 Commits

Author SHA1 Message Date
Scott Ashcroft e69341cd5f Make sure co-simulation only uses integer arithmetic 2026-04-23 17:22:14 +01:00
nella d795a4f1d2 Fix WASI, store in temp dir. 2026-04-23 12:43:43 +02:00
nella afac9a28b0 Fix WASI build. 2026-04-23 12:43:43 +02:00
nella 5d4d94a5dd Fix mac compile. 2026-04-23 12:43:43 +02:00
nella 94a215b4f7 Add dont_use_cells to scl cache. 2026-04-23 12:43:43 +02:00
nella edd3ad525e Add scl caching to abc_new. 2026-04-23 12:43:43 +02:00
nella 9143178343 Merge liberty files into stripped scl files. 2026-04-23 12:43:43 +02:00
N. Engelhardt 240f7030b2 xprop: ignore $scopeinfo cells 2026-04-21 10:52:50 +02:00
Emil J. Tywoniak b4c081c70b abc: fix deferred logs 2026-04-17 13:35:47 +02:00
nella 4506dffa9f Fix use after free. 2026-04-13 12:48:05 +02:00
nella fc71719e6e Rename csa_tree to arith_tree. 2026-04-13 12:48:05 +02:00
nella c3c577f333 Fix test cases. 2026-04-13 12:48:05 +02:00
nella 135812ab02 Further CSA cleanup. 2026-04-13 12:48:05 +02:00
nella 847a8941e9 Clang-Format CSA tree. 2026-04-13 12:48:05 +02:00
nella a02c238874 Consolidate Wallace from booth and CSA. 2026-04-13 12:48:05 +02:00
nella 4bbffecf98 Invert. 2026-04-13 12:48:05 +02:00
nella 42c309347b Clarify. 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak b6d656e932 csa_tree: move to techmap 2026-04-13 12:48:05 +02:00
Emil J. Tywoniak b6a8feec22 csa_tree: refactor 2026-04-13 12:48:05 +02:00
nella 67e145618b Replace utf arrow with ascii arrow. 2026-04-13 12:48:05 +02:00
nella 5d90bcc792 CSA add support for macc and alu cells. 2026-04-13 12:48:05 +02:00
nella 335cce4895 Add sub chain support for csa trees. 2026-04-13 12:48:05 +02:00
nella e69914b8be better balancing. 2026-04-13 12:48:05 +02:00
nella 46df888191 impl csa tree. 2026-04-13 12:48:05 +02:00
Lofty 564c617721
Merge pull request #5790 from Eiko-Eira/main 
Fixed typos and incorrect grammar
 2026-04-11 03:26:55 +00:00
Emil J 86448c0001
Merge pull request #5655 from YosysHQ/emil/dffsr-sr-priority-undef 
Undefine set&reset behavior of $dffsr
 2026-04-08 14:22:34 +00:00
Emil J. Tywoniak 41b69df2cb abc_new: stable TopoSort 2026-04-06 15:09:52 +02:00
Noah Van Dijk 52243e10fb
Fix typo in pmgen/README.md 
Line 161:
calulated > calculated
 2026-04-02 10:24:31 -05:00
Emil J cede13a742
Merge pull request #5765 from YosysHQ/emil/muxpack-wide-port 
muxpack: fix wide Y port handling
 2026-03-31 10:49:39 +00:00
tondapusili 5b22e64d19 sim: cache sigmap in register_output_step_values 2026-03-24 16:10:11 -07:00
Miodrag Milanović 66306a8ca3
Merge pull request #5769 from Silimate/optimize_sim_pass 
sim: early return from checkSignals in sim mode
 2026-03-23 17:19:26 +00:00
Emil J b44188110b
Merge pull request #5764 from YosysHQ/emil/constmap-error 
constmap: error if no -cell set
 2026-03-23 15:15:04 +00:00
tondapusili 69219e6be0 sim: early-return from checkSignals in sim mode 2026-03-20 12:32:49 -07:00
Lofty f560cba952
Merge pull request #5757 from YosysHQ/lofty/abc9-refactor-3 
abc9: remove -fast [sc-269]
 2026-03-19 08:41:45 +00:00
Lofty 27210627e5 abc9: remove -fast 2026-03-19 07:30:23 +00:00
Lofty 8d1d5a25e5
Merge pull request #5760 from YosysHQ/lofty/abc-refactor-2 
abc: remove -S [sc-269]
 2026-03-19 07:26:54 +00:00
Lofty 05de1c4ae2
Merge pull request #5759 from YosysHQ/lofty/abc9-refactor-4 
abc9: remove abc9.if.C [sc-269]
 2026-03-19 07:26:37 +00:00
Emil J. Tywoniak 4f4672d17b muxpack: fix wide Y port handling 2026-03-19 00:12:49 +01:00
Emil J. Tywoniak 7aaa0621d3 constmap: error if no -cell set 2026-03-19 00:01:14 +01:00
Emil J 9746bd3897
Merge pull request #5724 from abhinavputhran/fix/setundef-respect-selection 
setundef: respect selection for cells, processes, and connections
 2026-03-18 22:53:06 +00:00
Lofty f9d930ba5a
Revert "abc: remove -fast [sc-269]" 2026-03-18 17:55:17 +00:00
Lofty e05ed6b850
Merge pull request #5758 from YosysHQ/lofty/abc-refactor-1 
abc: remove -fast [sc-269]
 2026-03-18 15:09:36 +00:00
Lofty 0b3f103745 abc: remove -S 2026-03-18 14:40:23 +00:00
Lofty 93c762c7c1 abc9: remove abc9.if.C 2026-03-18 14:27:27 +00:00
Lofty 926814f1e4 abc9: cleanup commented code 2026-03-18 14:16:31 +00:00
Lofty 0ea739b7d9 abc: remove -fast 2026-03-18 14:15:42 +00:00
Lofty e78690fc47 abc9_exe: fix typo 2026-03-18 11:44:13 +00:00
Emil J c8f715fed8
Merge pull request #5664 from rocallahan/parallel-opt-clean 
Parallelize `opt_clean` pass
 2026-03-16 09:52:34 +00:00
Emil J. Tywoniak 498cb79abe async2sync: explain dffsr control signal variable polarity 2026-03-09 20:18:56 +01:00
Emil J. Tywoniak 43ef4d2901 fixup! async2sync: $dffsr has undef output on S&R 2026-03-09 20:12:24 +01:00
abhinavputhran 47c2257f82 setundef: more tests! and wire selection in -init mode 2026-03-08 19:41:31 -04:00
abhinavputhran 5048dac854 setundef: add tests for selection in -zero, -undriven, and -init modes. also made setundef.cc clearer 2026-03-06 18:12:03 -05:00
abhinavputhran 9e666c727f setundef: respect selection in -undriven mode 2026-03-06 10:37:59 -05:00
Miodrag Milanovic 52533b0d1c Update opt_lut_ins and stat for analogdevices and remove ecp5 2026-03-06 09:10:36 +01:00
Robert O'Callahan 9c51ba1b09 Reduce opt_clean parallelism 2026-03-06 02:20:16 +00:00
Robert O'Callahan 8d8c05b338 Fix `OptCleanPass` usage of `CleanRunContext` to avoid constructing extra `KeepCache` and `ParallelDispatchThreadPool` 2026-03-06 02:20:16 +00:00
Robert O'Callahan 32f5044eaf Clarify "Not passing module as function argument" comment 
This correct in terms of intent, it's just not fully enforced due to const laundering.
 2026-03-06 02:20:16 +00:00
Emil J. Tywoniak 70cc2d67fd opt_clean: refactor 2026-03-06 02:20:14 +00:00
Robert O'Callahan 3603cd52a0 Pass the module `Subpool` to `rmunused_module_signals` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 19a7c8fcf3 Pass the module `Subpool` to `rmunused_module_cells` and parallelize that function 2026-03-06 02:20:08 +00:00
Robert O'Callahan 8e044d1045 Pass the module `Subpool` to `rmunused_module_init` and parallelize that function 2026-03-06 02:20:06 +00:00
Robert O'Callahan a7437c636d Pass the toplevel thread pool to `rmunused_module`, create a `Subpool`, and parallelize `remove_temporary_cells` 2026-03-06 02:05:46 +00:00
Robert O'Callahan 887c32cb54 Create a toplevel `ParallelDispatchThreadPool` and parallelize `keep_cache_t::scan_module()` with it 2026-03-06 02:05:46 +00:00
Robert O'Callahan 72a21fe01d Introduce `RmStats` struct to encapsulate removal statistics 
Turns out this is not strictly necessary for this PR but it's
still a good thing to do and makes it clearer that the stats
are not modified in a possibly racy way.
 2026-03-06 02:05:43 +00:00
Robert O'Callahan c2bb7d6a82 Make `keep_cache_t` process all modules up-front instead of on-demand 
We will want to query `keep_cache` from parallel threads. If we compute
the results on-demand, that means we need synchronization for cache
access in those queries, which adds complexity and overhead. Instead, prefill
the cache with the status of all relevant modules. Note that this doesn't
actually do more work --- we always consult `keep_cache` for all cells of
all selected modules, so scanning all those cells and determining the kept
status of all dependency modules is always required.

Later in this PR we're going to parallelize `scan_module` itself, and that's also
much easier to do when no other parallel threads are running.
 2026-03-06 02:05:04 +00:00
abhinavputhran 6cd66aed47 setundef: rename process loop variable and respect selection in -init mode 2026-03-05 17:51:01 -05:00
abhinavputhran df283fa1c9 setundef: use selected_processes() per review feedback 2026-03-05 11:22:00 -05:00
abhinavputhran 4e54853e35 setundef: use selected_processes() per review feedback 2026-03-05 11:16:07 -05:00
abhinavputhran 94c789e9c8 setundef: respect selection for cells, processes, and connections 
Previously, setundef would rewrite sigspecs in all cells, processes,
and connections regardless of the active selection. Only modules and
memories were correctly filtered by selection.

Fix by using module->selected_cells() for cells, adding a
module->selected() check for processes, and checking wire selection
on the lhs of each connection before rewriting.

Fixes #5624
 2026-03-04 17:48:35 -05:00
Emil J 0d7a875675
Merge pull request #5512 from YosysHQ/emil/turbo-celltypes 
celltypes: compile-time lookup tables for internal cells
 2026-03-04 14:47:57 +00:00
nella 66bd4716cf rtlil use newcelltypes. 2026-03-04 12:39:45 +01:00
Emil J. Tywoniak ecb8b20f62 yosys: use newcelltypes for yosys_celltypes users 2026-03-04 12:39:44 +01:00
Emil J. Tywoniak 4ab22cbb97 abc: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 07ec8708e4 share: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 9e59f05c25 newcelltypes: wrap design celltypes support 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 35ccaa60d7 newcelltypes: TurboCellTypes -> StaticCellTypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 6adc08b0e5 opt_expr: use newcelltypes 2026-03-04 12:22:14 +01:00
Emil J. Tywoniak 3671d577a0 opt_clean: use newcelltypes 2026-03-04 12:22:14 +01:00
Miodrag Milanović 05d1d56b9d
Merge pull request #5704 from apullin/apullin/abc9-no-loops-fix 
abc9: preserve topological-loop asserts with targeted SCC fallback
 2026-03-04 11:09:38 +01:00
Miodrag Milanovic b7d013e6bf Fix help message for equiv passes 2026-03-04 07:46:40 +01:00
Tianji Liu 750d536bba abc: new option to pass ABC read_lib args 2026-03-04 11:24:24 +08:00
Emil J. Tywoniak 6f74c54c02 async2sync: $dffsr has undef output on S&R 2026-03-03 10:34:29 +01:00
Emil J. Tywoniak a53104379d clk2fflogic: $dffsr has undef output on S&R 2026-03-03 10:34:29 +01:00
KrystalDelusion 1d3f9b7905
Merge pull request #5687 from YosysHQ/nella/pdr-doc 
Update help text for rename -witness and write_aiger -ywmap
 2026-03-02 09:29:25 +13:00
Andrew Pullin 5970be33fb abc9: preserve topological-loop asserts with targeted SCC fallback 
A real-world ABC9 flow hit residual combinational loops after SCC breaking, tripping the prep_xaiger loop assertion.

Keep the existing topological assertions in place (prep_xaiger and reintegrate still assert no_loops).

To handle residual non-box loops, add a targeted fallback in prep_xaiger: when loops remain after normal SCC breaking, insert additional $__ABC9_SCC_BREAKER cuts on non-box loop cells, rebuild toposort, and then re-check the existing assertion.

Also keep pre-ABC9 SCC tagging on all cell types (scc -all_cell_types) and add a regression test (tests/techmap/abc9-nonbox-loop-with-box.ys).
 2026-02-26 22:30:32 -08:00
Emil J 5f8489d36d
Merge pull request #5666 from YosysHQ/emil/equiv_induct-missing-model-errors 
equiv_induct: error on missing model
 2026-02-25 15:39:31 +01:00
Miodrag Milanović 0ed7c5ad53
Merge pull request #5620 from YosysHQ/lofty/abc9-verify 
abc9: verify post-mapping equivalence by default
 2026-02-20 13:41:11 +01:00
Krystine Sherwin 094481739f memory_libmap: Add -force-params 
Reduce complexity for adi brams by unconditionally providing the WIDTH and ABITS parameters.
 2026-02-20 10:57:00 +00:00
nella 01e89a8f9e Remove cell mentions. 2026-02-18 09:29:35 +01:00
nella 2b4f481850 Cleanup docs. 2026-02-18 09:24:41 +01:00
Emil J. Tywoniak 77f64de997 satgen: move report_missing_model here from equiv.h 2026-02-16 17:01:09 +01:00
Emil J. Tywoniak 81ea922512 sat: use the same cell import warnings as equiv 2026-02-16 16:54:26 +01:00
nella e6e57b33e3 document abc --keep-going pdr [sc-220]. 2026-02-15 09:00:04 +01:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Emil J fba29ea8f1
Merge pull request #5679 from YosysHQ/emil/abc9-remove-liberty 
abc9: remove -liberty
 2026-02-11 12:36:29 +01:00
Emil J. Tywoniak 915912cc76 abc9: remove -dont_use 2026-02-11 11:39:09 +01:00
Emil J. Tywoniak c4094e457b abc9: remove -genlib, -constr 2026-02-11 11:34:54 +01:00
Emil J. Tywoniak 5a46106a46 abc9: remove -liberty 2026-02-11 01:04:50 +01:00
Gus Smith 6f6fa49d3c Typo 2026-02-09 09:05:56 -08:00
Gus Smith 1502e23371 Set solver from scratchpad or command line 2026-02-06 19:26:32 -08:00