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2188 Commits

Author SHA1 Message Date
Akash Levy 0b46d8b201
Merge pull request #109 from Silimate/clkgate_attr 
Added is_clock_gated attr to flops created via clockgate.cc pass
 2026-02-20 17:02:02 -08:00
AdvaySingh1 8f5b8cb46c Added is_clock_gated attr to flops created via clockgate.cc pass 2026-02-20 11:34:08 -08:00
AdvaySingh1 b29514fafc Added built in cell alongside sim support for cell 2026-02-19 11:48:35 -08:00
Akash Levy b7098e8383
Merge branch 'YosysHQ:main' into main 2026-02-18 09:44:25 -08:00
Gus Smith 29a270c4b6
Merge pull request #5675 from rowanG077/add-missing-celledges 
kernel/celledges: cover more cell types
 2026-02-18 07:50:41 -08:00
Akash Levy 5debd619e5 Add workaround for Liberty duplication 2026-02-13 06:51:42 -08:00
Akash Levy 0485576632 Revert rtlil changes 2026-02-13 04:14:14 -08:00
Akash Levy 2b247d165b Merge from main 2026-02-13 04:14:08 -08:00
Akash Levy b8d83c1d5b Fix cell naming issues 2026-02-13 01:05:51 -08:00
Gus Smith 8ab105ac28
Merge pull request #4303 from Coloquinte/sat_choice 
Infrastructure to run a Sat solver as a command
 2026-02-11 06:54:53 -08:00
Rowan Goemans b8ee50d77f kernel/celledges: cover more cell types 2026-02-09 14:13:40 +01:00
Gus Smith 1502e23371 Set solver from scratchpad or command line 2026-02-06 19:26:32 -08:00
Akash Levy f74ac17a5f Undo the terrible upstream changes that break everything... 2026-02-04 22:26:06 -08:00
Akash Levy d3ab45c2fa
Merge branch 'YosysHQ:main' into main 2026-02-04 15:53:43 -08:00
Emil J 2aa0e1d009
Merge pull request #5629 from rocallahan/remove-zero-wires 
Avoid scanning entire module in `Module::remove()` if there are no wires to remove
 2026-02-04 17:44:24 +01:00
Akash Levy 8e5d24aa6b Bump yosys to latest 2026-02-03 06:08:36 -08:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
Akash Levy 16087ae931 Merge from upstream 2026-01-28 18:17:50 -08:00
nella 8f6c4d40e4
Merge pull request #5623 from YosysHQ/nella/opt-dff-rewrite 
opt_dff restructure.
 2026-01-28 14:41:40 +01:00
Krystine Sherwin aaebce7adc
log_help: Don't reformat codeblocks 2026-01-28 08:07:44 +13:00
nella 9367090763 OptDff more accurate ctrl/pattern desc. 2026-01-26 22:19:36 +01:00
nella 5803461c24 opt_dff pattern extraction. 2026-01-26 22:10:10 +01:00
Robert O'Callahan dcd7742d52 Avoid scanning entire module if there are no wires to remove 
It's pretty common for `opt_clean` to find no wires to remove. In that case,
there is no point scanning the entire design, which can be significantly
expensive for huge designs.
 2026-01-23 01:38:20 +00:00
Akash Levy b11037e6c6 Merge remote-tracking branch 'upstream/main' 2026-01-21 15:13:57 -08:00
Robert O'Callahan 2c0448a81b Avoid spurious copy in `IdStringCollector::trace_named()` 2026-01-21 03:31:56 +00:00
Emil J. Tywoniak befadf6d4d consteval: describe 2026-01-19 12:00:18 +01:00
Natalia cf511628b0 modify generator for pyosys/wrappers.cc instead of headers 2026-01-18 02:11:09 -08:00
Akash Levy ef98c62bf2 Merge 2026-01-14 18:34:16 -08:00
Natalia fb864e91ee Add Design::run_pass() API for programmatic pass execution 
This commit adds a new run_pass() method to the RTLIL::Design class,
providing a convenient API for executing Yosys passes programmatically.

This is particularly useful for PyYosys users who want to run passes
on a design object without needing to manually construct Pass::call()
invocations. The method wraps Pass::call() with appropriate logging
to maintain consistency with command-line pass execution.

Example usage (from Python):
    design = ys.Design()
    # ... build or load design ...
    design.run_pass("hierarchy")
    design.run_pass("proc")
    design.run_pass("opt")

Changes:
- kernel/rtlil.h: Add run_pass() method declaration
- kernel/rtlil.cc: Implement run_pass() method
- tests/unit/kernel/test_design_run_pass.cc: Add unit tests
 2026-01-14 17:35:45 -08:00
nella 763001885f
Merge pull request #5608 from YosysHQ/nella/rtlil-to-string 
Add rtlil string getters
 2026-01-14 19:00:47 +01:00
nella 210b733555 Add rtlil string getters 2026-01-14 15:37:18 +01:00
Akash Levy a121255f47
Merge branch 'YosysHQ:main' into main 2026-01-13 11:28:34 -08:00
Emil J. Tywoniak 8e2038c419 Use digit separators for large decimal integers 2026-01-13 16:38:12 +01:00
Miodrag Milanovic 0e6973037d Update year in banner and license 2026-01-13 14:23:51 +01:00
Akash Levy 58192ad8a6
Merge branch 'YosysHQ:main' into main 2026-01-12 22:52:03 -08:00
Robert O'Callahan 8da919587d Parallelize `opt_merge`. 
I'm not sure why but this is actually faster than existing `opt_merge` even with
YOSYS_MAX_THREADS=1, for the jpeg synthesis test. 16.0s before, 15.5s after for
end-to-end synthesis.
 2026-01-08 04:21:39 +00:00
Akash Levy e332ba807d
Merge branch 'YosysHQ:main' into main 2026-01-07 12:40:39 -08:00
Emil J 0ab967b036
Merge pull request #5564 from rocallahan/pass-fuzz 
Add support for fuzz-test comparison of two passes intended to give identical RTLIL results
 2026-01-06 20:07:31 +01:00
Robert O'Callahan a6d696ba2b Give `IdString` a default move constructor and make it a POD type. 
Now that we're not refcounting `IdString`, it can use the default move constructor.
This lets us make `IdString` a POD type so it can be passed in registers
in the standard C++ ABI.
 2025-12-30 22:35:14 +00:00
Akash Levy 1941e8f042 Bump yosys and abc to latest 2025-12-25 03:46:16 -05:00
Robert O'Callahan 48cdb499f2 Remove `IdString::id_string()`. 
This was needed for the short time when `ID()` could return a value of `StaticIdString`.
That is no longer a problem.
 2025-12-22 01:57:30 +00:00
Robert O'Callahan 46cb05c471 Pass IdString by value instead of by const reference. 
When IdString refcounting was expensive, it made sense to pass it by const reference
instead of by value, to avoid refcount churn. Now that IdString is not refcounted,
it's slightly more efficient to pass it by value.
 2025-12-22 01:52:59 +00:00
Robert O'Callahan ddd6a16ee0 Add -legalize option to read_rtlil 2025-12-21 21:47:48 +00:00
Akash Levy abd485fa49 Bump Yosys to latest 2025-12-17 21:06:17 -08:00
Emil J f003eca615
Merge pull request #5526 from YosysHQ/emil/fix-cellaigs-function-arg-eval-order 
cellaigs: fix function argument evaluation order
 2025-12-12 10:00:09 +01:00
Emil J 5594b817cd
Merge pull request #5524 from rocallahan/single-thread-log 
Check that we don't use logging during multithreading
 2025-12-10 13:54:09 +01:00
Emil J e08e9119ee
Merge pull request #5516 from rocallahan/limit-threads 
Limit thread usage in tests
 2025-12-10 13:45:07 +01:00
Emil J. Tywoniak 99e873efc9 cellaigs: fix AOI and OAI ordering 2025-12-10 12:41:13 +01:00
Emil J. Tywoniak d932ce7f47 cellaigs: formatting 2025-12-10 12:33:17 +01:00
Emil J. Tywoniak 882001cb01 cellaigs: fix adder function argument evaluation order 2025-12-10 12:33:17 +01:00