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17,358 Commits 135 Branches 69 Tags 48 MiB
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17358 Commits

Author SHA1 Message Date
Emil J. Tywoniak 7c73fd62e4 twine: fix replayability, reduce TwineSearch usage 2026-06-22 17:53:19 +02:00
Emil J. Tywoniak e9eb3889b7 tests: skip broken 2026-06-22 17:42:04 +02:00
Emil J. Tywoniak ef4ed3ef15 twine: auto type WIP 2026-06-22 00:29:11 +02:00
Emil J. Tywoniak b27432326f WIP migration to twine 2026-06-22 00:27:32 +02:00
Emil J. Tywoniak 611b1bdfb4 techmap: fix twine reintern 2026-06-20 18:48:58 +02:00
Emil J. Tywoniak 84829cb11d rtlil_frontend: fix twine ordering 2026-06-20 18:16:47 +02:00
Emil J. Tywoniak 1b7daaae2e signorm: discard newly_driven capacity for performance 2026-06-20 18:09:10 +02:00
Emil J. Tywoniak d974527ab4 rtlil_frontend: allocate meta block 2026-06-19 11:48:44 +02:00
Emil J. Tywoniak e71ed3007d WIP migration to twine 2026-06-19 11:39:47 +02:00
Emil J. Tywoniak 54a3baa2de rtlil: fix twine handling 2026-06-19 11:39:47 +02:00
Emil J. Tywoniak 63043901ea twine: switch to std::deque from forked plf::colony 2026-06-19 11:39:47 +02:00
Emil J. Tywoniak bffe7a6e57 WIP migration to twine 2026-06-18 21:54:57 +02:00
Emil J. Tywoniak 0c450ce8c8 WIP migration to twine 2026-06-18 19:27:41 +02:00
Emil J. Tywoniak 96b0ba9581 WIP migration to twine 2026-06-17 11:04:03 +02:00
Emil J. Tywoniak 25f27026f0 newcelltypes: twines 2026-06-17 00:05:52 +02:00
Emil J. Tywoniak 44ce4c2356 opt: twines 2026-06-17 00:05:43 +02:00
Emil J. Tywoniak 7baf458ffe ff: twines 2026-06-16 23:16:36 +02:00
Emil J. Tywoniak 3a5f5c77bf twine: avoid TwinePool::lookup 2026-06-16 22:57:13 +02:00
Emil J. Tywoniak 4061593ce5 twine: GC again 2026-06-16 14:13:40 +02:00
Emil J. Tywoniak e5f6755ffd prevent IdString construction when looking up module from instance type 2026-06-16 13:16:18 +02:00
Emil J. Tywoniak 45c1654938 twine: GC again WIP 2026-06-16 13:15:39 +02:00
Emil J. Tywoniak eb7a55bb40 dump_twines: fix 2026-06-16 13:15:28 +02:00
Emil J. Tywoniak ec3e62cdfc dump_twines: fix 2026-06-16 13:15:20 +02:00
Emil J. Tywoniak 6f1ca02a90 rtlil_frontend, rtlil_backend: dump statics as strings, comments for src 2026-06-16 12:54:36 +02:00
Emil J. Tywoniak 9cb838febe twine: fix another off-by-one 2026-06-15 18:55:21 +02:00
Emil J. Tywoniak d96461e40c twine: fix off-by-one static twine error 2026-06-15 17:41:21 +02:00
Emil J. Tywoniak dcc74755e7 WIP 2026-06-15 11:26:09 +02:00
Emil J. Tywoniak d22805bd47 WIP 2026-06-12 16:25:07 +02:00
Emil J. Tywoniak c3ffbf6fae WIP 2026-06-12 00:18:53 +02:00
Emil J. Tywoniak afdae7b87e WIP 2026-06-11 20:02:02 +02:00
Emil J. Tywoniak 8e522b08c0 WIP 2026-06-11 13:17:54 +02:00
Emil J. Tywoniak f592f2f3af WIP 2026-06-10 19:22:53 +02:00
Emil J. Tywoniak 015ab4e45b twine: start indexable colony with integer indices including preallocated twines 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak 8ab96a4285 BROKEN 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak 2117af318c WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak d13dfc21f4 WIP 2026-06-10 14:54:48 +02:00
Emil J. Tywoniak 1a8a95b472 rtlil: fix masquerade 2026-06-10 14:54:45 +02:00
Emil J. Tywoniak 2d3b7e9c92 rtlil: introduce ModuleNameMasq (KNOWN BROKEN, do not merge) 2026-06-10 14:54:43 +02:00
Emil J. Tywoniak e2627b367e rtlil: set Module::design before name at all construction sites 2026-06-10 14:54:39 +02:00
Emil J. Tywoniak 734593e12d rtlil: Module::clone attaches to source design; callers use clone(dst) 2026-06-10 14:54:34 +02:00
Emil J. Tywoniak 8f8a07efee rtlil: replace AttrObject::meta_idx_ with ObjMeta pointer 2026-06-10 14:54:31 +02:00
Emil J. Tywoniak cfd7edc608 Patch: route staged cell names through per-Patch dict 2026-06-10 14:54:27 +02:00
Emil J. Tywoniak 0f31d3089e rtlil: extend per-Design meta vector to hold name slot 2026-06-10 14:54:16 +02:00
Emil J. Tywoniak ca632e82c4 rtlil: set Module* on inner-process AttrObjects at construction 2026-06-10 14:54:12 +02:00
Emil J. Tywoniak f1edb571f2 rtlil: evacuate src_id_ from AttrObject to per-Design meta vector 2026-06-10 14:54:05 +02:00
Emil J. Tywoniak e70eed3296 rtlil: add Module* back-pointer to RTLIL::Memory 2026-06-10 14:53:59 +02:00
Emil J. Tywoniak 9ed93e210b rtlil: add per-Design src meta vector + freelist 2026-06-10 14:53:55 +02:00
Emil J. Tywoniak 29ab42bc4e rtlil: add Module* back-pointer to inner-process AttrObjects 2026-06-10 14:53:48 +02:00
Emil J. Tywoniak 3424c00cd0 twine 2026-06-10 14:53:45 +02:00
Emil J. Tywoniak 3d27e83d0f memory_map: propagate Mem src onto every generated cell 2026-06-10 14:53:42 +02:00