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WIP migration to twine

This commit is contained in:
Emil J. Tywoniak 2026-06-19 11:37:12 +02:00
parent 54a3baa2de
commit e71ed3007d
8 changed files with 49 additions and 55 deletions
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4
backends/rtlil/rtlil_backend.cc
View File

@ -61,8 +61,8 @@ void RTLIL_BACKEND::dump_twines(std::ostream &f, const RTLIL::Design *design)
return;
f << stringf("twines\n");
std::vector<TwineRef> ids;
for (auto it = design->twines.backing.begin(); it != design->twines.backing.end(); ++it)
ids.push_back(STATIC_TWINE_END + design->twines.backing.get_index(it));
for (size_t idx = 0; idx < design->twines.backing.size(); ++idx)
ids.push_back(STATIC_TWINE_END + idx);
std::sort(ids.begin(), ids.end());
for (TwineRef id : ids) {
const Twine &n = design->twines[id];

51
frontends/aiger/aigerparse.cc
View File

@ -223,7 +223,7 @@ AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString
{
module = new RTLIL::Module;
module->design = design;
module->meta_->name = design->twines.add(Twine{module_name.str()});
module->meta_->name = design->twines.add(std::string{module_name.str()});
if (design->module(module->meta_->name))
log_error("Duplicate definition of module %s!\n", design->twines.str(module->meta_->name).c_str());
}
@ -307,7 +307,7 @@ end_of_header:
wire = bad_properties[l1];
} else log_abort();
module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
module->rename(wire, design->twines.add(std::string{escaped_s.str()}));
}
else if (c == 'j' || c == 'f') {
// TODO
@ -350,7 +350,7 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(wire_name.str()));
if (wire) return wire;
log_debug2("Creating %s\n", wire_name.c_str());
wire = module->addWire(Twine{wire_name.str()});
wire = module->addWire(design->twines.add(std::string{wire_name.str()}));
wire->port_input = wire->port_output = false;
if (!invert) return wire;
RTLIL::IdString wire_inv_name(stringf("$aiger%d$%d", aiger_autoidx, variable));
@ -360,7 +360,7 @@ RTLIL::Wire* AigerReader::createWireIfNotExists(RTLIL::Module *module, unsigned
}
else {
log_debug2("Creating %s\n", wire_inv_name.c_str());
wire_inv = module->addWire(Twine{wire_inv_name.str()});
wire_inv = module->addWire(design->twines.add(std::string{wire_inv_name.str()}));
wire_inv->port_input = wire_inv->port_output = false;
}
@ -504,10 +504,10 @@ void AigerReader::parse_xaiger()
uint32_t boxUniqueId = parse_xaiger_literal(f);
log_assert(boxUniqueId > 0);
uint32_t oldBoxNum = parse_xaiger_literal(f);
TwineRef _type = module->design->twines.add(Twine{stringf("$__boxid%u", boxUniqueId)});
TwineRef _type = module->design->twines.add(std::string{stringf("$__boxid%u", boxUniqueId)});
RTLIL::Cell* cell = module->addCell(Twine{stringf("$box%u", oldBoxNum)}, _type);
cell->setPort(TW::I, SigSpec(State::S0, boxInputs));
cell->setPort(TW::O, SigSpec(State::S0, boxOutputs));
cell->setPort(TW::i, SigSpec(State::S0, boxInputs));
cell->setPort(TW::o, SigSpec(State::S0, boxOutputs));
cell->attributes[ID::abc9_box_seq] = oldBoxNum;
boxes.emplace_back(cell);
}
@ -551,7 +551,7 @@ void AigerReader::parse_aiger_ascii()
clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
log_assert(!clk_wire);
log_debug2("Creating %s\n", clk_name.c_str());
clk_wire = module->addWire(Twine{clk_name.str()});
clk_wire = module->addWire(design->twines.add(std::string{clk_name.str()}));
clk_wire->port_input = true;
clk_wire->port_output = false;
}
@ -678,7 +678,7 @@ void AigerReader::parse_aiger_binary()
clk_wire = module->wire(TwineSearch(&design->twines).find(clk_name.str()));
log_assert(!clk_wire);
log_debug2("Creating %s\n", clk_name.c_str());
clk_wire = module->addWire(Twine{clk_name.str()});
clk_wire = module->addWire(design->twines.add(std::string{clk_name.str()}));
clk_wire->port_input = true;
clk_wire->port_output = false;
}
@ -776,7 +776,7 @@ void AigerReader::post_process()
{
unsigned ci_count = 0, co_count = 0;
for (auto cell : boxes) {
for (auto &bit : cell->connections_.at(TW::I)) {
for (auto &bit : cell->connections_.at(TW::i)) {
log_assert(bit == State::S0);
log_assert(co_count < outputs.size());
bit = outputs[co_count++];
@ -784,7 +784,7 @@ void AigerReader::post_process()
log_assert(bit.wire->port_output);
bit.wire->port_output = false;
}
for (auto &bit : cell->connections_.at(TW::O)) {
for (auto &bit : cell->connections_.at(TW::o)) {
log_assert(bit == State::S0);
log_assert((piNum + ci_count) < inputs.size());
bit = inputs[piNum + ci_count++];
@ -832,7 +832,7 @@ void AigerReader::post_process()
// simply connect the latter to the former
existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
module->rename(wire, design->twines.add(std::string{escaped_s.str()}));
else {
wire->port_input = false;
module->connect(wire, existing);
@ -843,7 +843,7 @@ void AigerReader::post_process()
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{indexed_name.str()}));
module->rename(wire, design->twines.add(std::string{indexed_name.str()}));
else {
module->connect(wire, existing);
wire->port_input = false;
@ -877,7 +877,7 @@ void AigerReader::post_process()
// simply connect the latter to the former
existing = module->wire(TwineSearch(&design->twines).find(escaped_s.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{escaped_s.str()}));
module->rename(wire, design->twines.add(std::string{escaped_s.str()}));
else {
wire->port_output = false;
existing->port_output = true;
@ -890,7 +890,7 @@ void AigerReader::post_process()
RTLIL::IdString indexed_name = stringf("%s[%d]", escaped_s, index);
existing = module->wire(TwineSearch(&design->twines).find(indexed_name.str()));
if (!existing)
module->rename(wire, design->twines.add(Twine{indexed_name.str()}));
module->rename(wire, design->twines.add(std::string{indexed_name.str()}));
else {
wire->port_output = false;
existing->port_output = true;
@ -916,7 +916,7 @@ void AigerReader::post_process()
if (!cell)
log_debug("Box %d (%s) no longer exists.\n", variable, log_id(escaped_s));
else
module->rename(cell, design->twines.add(Twine{escaped_s.str()}));
module->rename(cell, design->twines.add(std::string{escaped_s.str()}));
}
else
log_error("Symbol type '%s' not recognised.\n", type);
@ -932,7 +932,7 @@ void AigerReader::post_process()
RTLIL::Wire *wire = module->wire(TwineSearch(&design->twines).find(name.str()));
if (wire)
module->rename(wire, design->twines.add(Twine{RTLIL::escape_id(stringf("%s[%d]", name.str(), 0))}));
module->rename(wire, design->twines.add(std::string{RTLIL::escape_id(stringf("%s[%d]", name.str(), 0))}));
// Do not make ports with a mix of input/output into
// wide ports
@ -946,7 +946,7 @@ void AigerReader::post_process()
}
}
wire = module->addWire(Twine{name.str()}, max-min+1);
wire = module->addWire(design->twines.add(std::string{name.str()}), max-min+1);
wire->start_offset = min;
wire->port_input = port_input;
wire->port_output = port_output;
@ -967,23 +967,18 @@ void AigerReader::post_process()
module->fixup_ports();
// Insert into a new (temporary) design so that "clean" will only
// operate (and run checks on) this one module
RTLIL::Design *mapped_design = new RTLIL::Design;
mapped_design->add(module);
Pass::call(mapped_design, "clean");
mapped_design->modules_.erase(module->meta_->name);
delete mapped_design;
// Run "clean" scoped to just this module. Moving it to a throwaway design
// would dangle its names, since the twine refs live in this design's pool.
design->add(module);
Pass::call_on_module(design, module, "clean");
for (auto cell : module->cells().to_vector()) {
if (cell->type != TW($lut)) continue;
auto y_port = cell->getPort(TW::Y).as_bit();
if (y_port.wire->width == 1)
module->rename(cell, design->twines.add(Twine{stringf("$lut%s", design->twines.str(y_port.wire->meta_->name).c_str())}));
module->rename(cell, design->twines.add(std::string{stringf("$lut%s", design->twines.str(y_port.wire->meta_->name).c_str())}));
else
module->rename(cell, design->twines.add(Twine{stringf("$lut%s[%d]", design->twines.str(y_port.wire->meta_->name).c_str(), y_port.offset)}));
module->rename(cell, design->twines.add(std::string{stringf("$lut%s[%d]", design->twines.str(y_port.wire->meta_->name).c_str(), y_port.offset)}));
}
}

6
passes/cmds/dump_twines.cc
View File

@ -41,9 +41,9 @@ struct DumpTwinesPass : public Pass {
const TwinePool &pool = design->twines;
log("twine pool: %zu local nodes\n", pool.size());
for (auto it = pool.backing.begin(); it != pool.backing.end(); ++it) {
TwineRef id = STATIC_TWINE_END + pool.backing.get_index(it);
const Twine &n = *it;
for (size_t idx = 0; idx < pool.backing.size(); ++idx) {
TwineRef id = STATIC_TWINE_END + idx;
const Twine &n = pool.backing[idx];
if (n.is_leaf()) {
log(" @%zu leaf \"%s\"", (size_t)id, n.leaf().c_str());
} else if (n.is_suffix()) {

16
passes/cmds/select.cc
View File

@ -685,7 +685,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char
static void select_filter_active_mod(RTLIL::Design *design, RTLIL::Selection &sel)
{
if (!design->selected_active_module)
if (design->selected_active_module == Twine::Null)
return;
if (sel.full_selection) {
@ -848,7 +848,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp
select_blackboxes = true;
}
if (design->selected_active_module) {
if (design->selected_active_module != Twine::Null) {
arg_mod = design->twines.str(design->selected_active_module);
arg_memb = arg;
if (!isprefixed(arg_memb))
@ -1524,7 +1524,7 @@ struct SelectPass : public Pass {
if (clear_mode) {
design->selection() = RTLIL::Selection::FullSelection(design);
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
return;
}
@ -1733,7 +1733,7 @@ struct CdPass : public Pass {
if (args.size() == 1 || args[1] == "/") {
design->pop_selection();
design->push_full_selection();
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
return;
}
@ -1743,7 +1743,7 @@ struct CdPass : public Pass {
design->pop_selection();
design->push_full_selection();
design->selected_active_module = TwineRef{};
design->selected_active_module = Twine::Null;
TwineSearch search(&design->twines);
while (1)
@ -1774,10 +1774,10 @@ struct CdPass : public Pass {
TwineSearch search(&design->twines);
TwineRef modname = search.find(RTLIL::escape_id(args[1]));
if (design->module(modname) == nullptr && design->selected_active_module) {
if (design->module(modname) == nullptr && design->selected_active_module != Twine::Null) {
RTLIL::Module *module = design->module(design->selected_active_module);
TwineRef cell_ref = modname;
if (module != nullptr && cell_ref && module->cell(cell_ref) != nullptr)
if (module != nullptr && cell_ref != Twine::Null && module->cell(cell_ref) != nullptr)
modname = module->cell(cell_ref)->type_impl;
}
@ -1837,7 +1837,7 @@ struct LsPass : public Pass {
size_t argidx = 1;
extra_args(args, argidx, design);
if (!design->selected_active_module)
if (design->selected_active_module == Twine::Null)
{
std::vector<IdString> matches;

11
passes/equiv/equiv_make.cc
View File

@ -108,13 +108,13 @@ struct EquivMakeWorker
for (auto it : gold_clone->wires().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
wire_names.insert(it->name);
gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
gold_clone->rename(it, gold_clone->design->twines.add(std::string{it->name.str() + "_gold"}));
}
for (auto it : gold_clone->cells().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gold_clone->rename(it, gold_clone->design->twines.add(Twine{it->name.str() + "_gold"}));
gold_clone->rename(it, gold_clone->design->twines.add(std::string{it->name.str() + "_gold"}));
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
gold_clone->remove(it);
}
@ -122,13 +122,13 @@ struct EquivMakeWorker
for (auto it : gate_clone->wires().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
wire_names.insert(it->name);
gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
gate_clone->rename(it, gate_clone->design->twines.add(std::string{it->name.str() + "_gate"}));
}
for (auto it : gate_clone->cells().to_vector()) {
if ((it->name.isPublic() || inames) && blacklist_names.count(it->name) == 0)
cell_names.insert(it->name);
gate_clone->rename(it, gate_clone->design->twines.add(Twine{it->name.str() + "_gate"}));
gate_clone->rename(it, gate_clone->design->twines.add(std::string{it->name.str() + "_gate"}));
if (it->type.in(TW($input_port), TW($output_port), TW($public)))
gate_clone->remove(it);
}
@ -516,9 +516,8 @@ struct EquivMakePass : public Pass {
log_header(design, "Executing EQUIV_MAKE pass (creating equiv checking module).\n");
worker.equiv_mod = design->addModule(design->twines.add(Twine{RTLIL::escape_id(args[argidx+2])}));
worker.equiv_mod = design->addModule(design->twines.add(std::string{RTLIL::escape_id(args[argidx+2])}));
worker.run();
Pass::call(design, "dump");
}
} EquivMakePass;

2
passes/hierarchy/flatten.cc
View File

@ -350,7 +350,7 @@ struct FlattenWorker
RTLIL::Cell *cell = worklist.back();
worklist.pop_back();
TwineRef cell_type_ref = design->twines.add(Twine{cell->type.str()});
TwineRef cell_type_ref = cell->type.ref();
if (!design->has(cell_type_ref))
continue;

2
passes/memory/memory_map.cc
View File

@ -263,7 +263,7 @@ struct MemoryMapWorker
if (module->wire(TwineSearch(&design->twines).find(w_out_name)) != nullptr)
w_out_name = genid(mem.memid, "", addr, "$q");
RTLIL::Wire *w_out = module->addWire(design->twines.add(Twine{w_out_name}), mem.width);
RTLIL::Wire *w_out = module->addWire(design->twines.add(std::string{w_out_name}), mem.width);
if (formal && mem.packed && mem.cell->name.isPublic()) {
auto hdlname = mem.cell->get_hdlname_attribute();

12
passes/sat/miter.cc
View File

@ -146,7 +146,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
{
if (gold_cross_ports.count(gold_wire))
{
SigSpec w = miter_module->addWire(Twine{"\\cross_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
SigSpec w = miter_module->addWire(design->twines.add(std::string{"\\cross_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
gold_cell->setPort(gold_wire->meta_->name, w);
if (flag_ignore_gold_x) {
RTLIL::SigSpec w_x = miter_module->addWire(NEW_TWINE, GetSize(w));
@ -162,7 +162,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (gold_wire->port_input)
{
RTLIL::Wire *w = miter_module->addWire(Twine{"\\in_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
RTLIL::Wire *w = miter_module->addWire(design->twines.add(std::string{"\\in_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
w->port_input = true;
gold_cell->setPort(gold_wire->meta_->name, w);
@ -171,10 +171,10 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (gold_wire->port_output)
{
RTLIL::Wire *w_gold = miter_module->addWire(Twine{"\\gold_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
RTLIL::Wire *w_gold = miter_module->addWire(design->twines.add(std::string{"\\gold_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
w_gold->port_output = flag_make_outputs;
RTLIL::Wire *w_gate = miter_module->addWire(Twine{"\\gate_" + design->twines.str(gold_wire->meta_->name)}, GetSize(gold_wire));
RTLIL::Wire *w_gate = miter_module->addWire(design->twines.add(std::string{"\\gate_" + design->twines.unescaped_str(gold_wire->meta_->name)}), GetSize(gold_wire));
w_gate->port_output = flag_make_outputs;
gold_cell->setPort(gold_wire->meta_->name, w_gold);
@ -247,7 +247,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_outcmp)
{
RTLIL::Wire *w_cmp = miter_module->addWire(Twine{"\\cmp_" + design->twines.str(gold_wire->meta_->name)});
RTLIL::Wire *w_cmp = miter_module->addWire(design->twines.add(std::string{"\\cmp_" + design->twines.unescaped_str(gold_wire->meta_->name)}));
w_cmp->port_output = true;
miter_module->connect(RTLIL::SigSig(w_cmp, this_condition));
}
@ -255,7 +255,7 @@ void create_miter_equiv(struct Pass *that, std::vector<std::string> args, RTLIL:
if (flag_make_cover)
{
auto cover_condition = miter_module->Not(NEW_TWINE, this_condition);
miter_module->addCover(Twine{"\\cover_" + design->twines.str(gold_wire->meta_->name)}, cover_condition, State::S1);
miter_module->addCover(Twine{"\\cover_" + design->twines.unescaped_str(gold_wire->meta_->name)}, cover_condition, State::S1);
}
all_conditions.append(this_condition);