nella
666df5e9c8
Test boundary cells.
2026-09-21 16:33:47 +02:00
nella
ed8b0bf9f7
Test port corner cases.
2026-09-21 16:33:47 +02:00
nella
8955e0fe7a
Add abc_new tests.
2026-09-21 16:33:47 +02:00
Miodrag Milanović
7b5eba489c
Merge pull request #6229 from YosysHQ/micko/update_abc
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Update ABC as per 2026-09-21
2026-09-21 13:54:39 +00:00
Miodrag Milanovic
f3159c72cb
Update ABC as per 2026-09-21
2026-09-21 13:53:37 +02:00
N. Engelhardt
950ac95e85
Merge pull request #6226 from YosysHQ/krys/contributing_formatting
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contributing.rst: Fixing up formatting
2026-09-21 08:33:10 +00:00
N. Engelhardt
2d2f2cfede
Merge pull request #6160 from YosysHQ/itsaflower-patch-2
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Add AI policy
2026-09-21 08:33:02 +00:00
Krystine Sherwin
1cf1c5f02d
contributing.rst: Fixing up formatting
2026-09-21 20:03:30 +12:00
Krystine Sherwin
92d6ae7fb7
docs: Link to interim LLM policy
2026-09-21 20:03:30 +12:00
itsaflower
64233b1cc1
Update CONTRIBUTING.md
2026-09-21 20:03:30 +12:00
Catherine
9ff27d29c6
Merge pull request #6212 from YosysHQ/mmicko/yosys_python_executable
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cmake: do not alter name in yosys_python_executable
2026-09-20 14:44:58 +00:00
Miodrag Milanović
f0b945f63c
Merge pull request #6213 from YosysHQ/mmicko/shutdown_win
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Execute clean shutdown on windows as well
2026-09-18 06:25:07 +00:00
Miodrag Milanovic
656f62b337
Execute clean shutdown on windows as well
2026-09-18 08:06:51 +02:00
Miodrag Milanovic
cdee781597
cmake: do not alter name in yosys_python_executable
2026-09-17 12:06:07 +02:00
Miodrag Milanović
2e7d8006da
Merge pull request #6211 from YosysHQ/mmicko/abc_update
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Update ABC as per 2026-09-17
2026-09-17 06:58:35 +00:00
Miodrag Milanovic
ff67a82a13
Update ABC as per 2026-09-17
2026-09-17 08:38:40 +02:00
Emil J
150c32b03e
Merge pull request #6154 from YosysHQ/emil/liberty-filter
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liberty: add filtering for things we need
2026-09-16 16:44:09 +00:00
Emil J. Tywoniak
91ac95c2b4
libparse: overwrite cache whenever old filter doesn't cover new filter
2026-09-16 18:21:46 +02:00
nella
9e8f12b9b3
Merge pull request #6207 from YosysHQ/nella/xilinx-rdfirst-xc7
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xilinx: fix BRAM mapping for negedge port next to READ_FIRST port [sc-917]
2026-09-16 13:14:35 +00:00
Lofty
92f43919b3
Merge pull request #6206 from YosysHQ/lofty/add-xaiger2-test
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xaiger2: add testcase from #4349
2026-09-16 13:07:30 +00:00
Emil J
d5e9476d2b
Merge pull request #6208 from YosysHQ/emil/nix-macos-symlink-share
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yosys: fix share path on MacOS when behind a symlink
2026-09-16 13:04:27 +00:00
Emil J. Tywoniak
716ee4d47a
yosys: fix share path on MacOS when behind a symlink
2026-09-16 13:57:26 +02:00
nella
a651db986a
xilinx: Drop READ_FIRST erratum on 7 series.
2026-09-16 09:14:50 +02:00
Lofty
415dfc0960
xaiger2: add testcase from #4349
2026-09-16 08:13:23 +01:00
nella
0edda7a3ab
Merge pull request #6201 from YosysHQ/nella/check-internal-celltypes
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check: reject unknown internal cell types [sc-915]
2026-09-15 11:52:15 +00:00
Lofty
d85872386a
Merge pull request #6174 from YosysHQ/lofty/abc-refactor-16
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abc9: migrate to write_xaiger2
2026-09-14 16:25:07 +00:00
Miodrag Milanović
f04d70bd9b
Merge pull request #6200 from YosysHQ/mmicko/heredoc
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Use <inlined> for heredoc input filename
2026-09-14 14:50:38 +00:00
Emil J
a9888845d2
Merge pull request #6194 from YosysHQ/emil/abc-module-and-clkdomain-par
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abc: module and clock domain parallelism, always
2026-09-14 13:29:38 +00:00
nella
76213a5d4c
Reject unknown internal cell types in check and hierarchy -check.
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A $-prefixed cell type must be a known cell type or a module in the
design. check reports it as a problem, hierarchy -check errors.
2026-09-14 13:50:09 +02:00
nella
77bca709d4
Declare synth_fabulous pad cells as blackboxes.
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iopadmap inserted $__FABULOUS_* cells with no module, so their port
directions were unknown to later passes. Read with -icells so the module
names match the cell types.
2026-09-14 13:50:09 +02:00
Emil J. Tywoniak and Jakub Michalski
72b30b1820
abc: dispatch modules in cell count order
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Co-authored-by: Jakub Michalski <[email protected] >
2026-09-14 12:52:10 +02:00
Miodrag Milanovic
5cdba4fbd7
Update tests to reflect change to <inlined>
2026-09-14 10:35:11 +02:00
Miodrag Milanovic
e091c16539
Use <inlined> for heredoc input filename
2026-09-14 10:16:34 +02:00
Miodrag Milanović
d0e71cfb7b
Merge pull request #6173 from YosysHQ/mmicko/colored
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log: Colored output for console
2026-09-11 11:27:21 +00:00
Emil J. Tywoniak
5a81ce51c0
fixup! abc: finish the submitted runs before propagating an error
2026-09-11 10:08:28 +02:00
Miodrag Milanović
6d10de1bc4
Merge pull request #6197 from YosysHQ/update_abc
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Update ABC as per 2026-09-11
2026-09-11 07:25:26 +00:00
Miodrag Milanovic
c595ef69c6
Update ABC as per 2026-09-11
2026-09-11 08:37:38 +02:00
Emil J. Tywoniak
60a7f254f8
tests: rebless blif gatesi cell order
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
bc92c9d9bf
abc: finish the submitted runs before propagating an error
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
cc9d6389d6
tests: rebless gatemate cell counts
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
5c6c0f66e3
abc: re-isolate autoidx churn
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
fa61f1732e
abc: clock domain parallelism is module parallelism
2026-09-10 18:16:57 +02:00
Emil J. Tywoniak
2a1c20dbbe
liberty: add filtering for things we need
2026-09-10 16:12:49 +02:00
Miodrag Milanović
3a82894842
Merge pull request #6100 from YosysHQ/mmicko/test_verific
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tests: Explicitly run tests without and with Verific where applicable
2026-09-10 10:07:07 +00:00
Miodrag Milanović
87b17517fd
Merge pull request #6188 from YosysHQ/revert-6182-lofty/revert-read_xaiger2
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Revert "Temporarily revert #6101 and #6077 "
2026-09-10 09:17:02 +00:00
Miodrag Milanović
13b9011887
Merge pull request #5705 from YosysHQ/gus/rename-symbiyosys-to-sby
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Rename SymbiYosys to SBY
2026-09-10 08:49:58 +00:00
Miodrag Milanovic
ec25ee4de8
Fix remaining mentions, and update links
2026-09-10 10:24:34 +02:00
Gus Smith
dcbf68bd5b
Fix docs/Makefile filename renames
2026-09-10 10:08:50 +02:00
Gus Smith
697fed66da
Rename SymbiYosys to SBY
2026-09-10 10:08:49 +02:00
Miodrag Milanović
ae86bbb130
Revert "Temporarily revert #6101 and #6077 "
2026-09-10 09:09:13 +02:00