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2210 Commits

Author SHA1 Message Date
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
KrystalDelusion 489a12d6c1
Merge pull request #5141 from garytwong/unique-if 
Accept (and ignore) SystemVerilog unique/priority if.
 2025-05-27 09:45:50 +12:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Gary Wong 73e45d29d6 Add semantic test cases for SystemVerilog priority/unique/unique0 "if". 
The tests/verilog/*_if_enc.ys scripts instantiate simple encoder
modules, both with and without the SystemVerilog priority/unique/unique0
keywords, and check for consistency between the two for the subset
of inputs where the priority/unique/unique0 "if" result is
well-defined.

These tests vacuously succeed at the moment, since priority/unique
keywords are silently ignored and therefore the generated logic is
trivially identical.  But the test cases will be capable of detecting
certain types of unsound optimisation if priority/unique handling is
introduced later.
 2025-05-24 08:44:04 -06:00
Emil J 18abf2d4f7
Merge pull request #5138 from YosysHQ/emil/libcache-verbose 
libcache: add -quiet and -verbose
 2025-05-24 00:05:46 +02:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
Akash Levy d520cb42cc
Merge branch 'YosysHQ:main' into main 2025-05-22 10:30:58 -07:00
George Rennie 6331f92d00
Merge pull request #5101 from georgerennie/george/opt_expr_shift_ovfl 
opt_expr: fix shift optimization with overflowing shift amount
 2025-05-22 15:16:19 +01:00
Akash Levy 3f94486a1c
Merge pull request #82 from donn/splitlarge 
splitlarge: new pass to split wide arithmetic operators
 2025-05-15 15:00:45 -07:00
Akash Levy 1f00bf0057 Bump yosys to latest 2025-05-15 14:44:26 -07:00
KrystalDelusion 4c72b0ecd8
Merge pull request #5116 from YosysHQ/krys/update_fst 
Update fstlib
 2025-05-16 09:22:52 +12:00
KrystalDelusion f7888c607b
Merge pull request #5089 from YosysHQ/krys/cutpoint_whole 
cutpoint: Re-add whole module optimization
 2025-05-16 09:22:28 +12:00
Mohamed Gaber 1d9fbb6143 misc: review feedback, remove MUL vestiges 2025-05-15 18:01:13 +03:00
Mohamed Gaber 46ba89059a splitlarge: new pass to split wide arithmetic operators 
Adds a new pass, `splitlarge`, that recursively divides $add/$sub
cells into smaller cells until each cell's width doesn't exceed a
given max_width (128 by default.) An $add/$sub cell's width for
this purpose is defined as the higher of the widths of its two
inputs.

A test was written in Tcl for it, which tests this matrix:
- cell: $add/$sub
- b: unsigned, signed
- a: unsigned, signed

This is the first test for a Silimate pass in Tcl and thus
`run-test.sh` was modified to include it.
 2025-05-15 17:45:08 +03:00
Emil J 3823157c25
Merge pull request #5080 from akashlevy/muldiv_c 
Add `muldiv_c` peepopt
 2025-05-15 11:03:25 +02:00
Akash Levy ccc2ba41f2
Merge branch 'YosysHQ:main' into main 2025-05-12 15:02:55 -07:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin afd5bbc7fa
fstdata.cc: Fix last step 
Includes test file for sanity checking simulation steps.
 2025-05-12 13:18:19 +12:00
williamzhu17 fc86bd8e74 finalized tests 2025-05-11 11:16:50 -07:00
williamzhu17 39be4f29bd opt_balance_tree test cases 2025-05-11 10:58:29 -07:00
williamzhu17 51a951d614 wip tests 2025-05-11 10:17:08 -07:00
williamzhu17 e0714ca714 Merge branch 'main' into opt_balance_tree-tests 2025-05-11 09:07:17 -07:00
Adrien Prost-Boucle 6bf7587338 URAM mapping : Add test for 2048 x 144b 2025-05-10 14:53:56 +02:00
Emil J. Tywoniak 9d2f9f7557 libcache: fix test 2025-05-09 12:40:38 +02:00
Akash Levy b88cff68d7
Merge pull request #79 from williamzhu17/new-muxorder-tests 
Added new muxorder tests
 2025-05-08 17:40:55 -07:00
williamzhu17 b265ea9dcf removed comma 2025-05-08 17:39:16 -07:00
williamzhu17 8d20ed0637 updated tests a bit 2025-05-08 17:38:42 -07:00
williamzhu17 d10e42c4bf added some tests 2025-05-08 17:36:35 -07:00
williamzhu17 82fa68aa2d added new muxorder tests 2025-05-08 14:05:13 -07:00
George Rennie d59380b3a0 tests: more complete testing of shift edgecases 2025-05-08 11:09:01 +02:00
George Rennie af933b4f38 tests: check shifts by amounts that overflow int 2025-05-07 15:12:33 +02:00
Akash Levy 7191be492c
Merge branch 'YosysHQ:main' into main 2025-05-05 15:36:40 -07:00
Krystine Sherwin 7c89355b70
cutpoint: Re-add whole module optimization 
Also add a test script for it.
 2025-05-06 09:57:34 +12:00
Krystine Sherwin 7c2b00c448
tests: Add default param test file 
Just loads, fails ASAN without fix.
 2025-05-05 10:18:52 +12:00
Akash Levy 4bd91fbb11 Add `muldiv_c` peepopt pass 2025-04-30 08:06:59 -07:00
Akash Levy 5e0d59ca90
Merge branch 'YosysHQ:main' into main 2025-04-28 18:12:42 -07:00
KrystalDelusion bfe05965f9
Merge pull request #5066 from YosysHQ/george/opt_expr_shr_sign 
opt_expr: fix sign extension for shifts
 2025-04-29 09:29:10 +12:00
Akash Levy 618cf9d372
Merge branch 'YosysHQ:main' into main 2025-04-28 13:57:29 -07:00
N. Engelhardt 84c49e1f33
Merge pull request #5041 from jix/declockgate-v2 2025-04-28 13:31:11 +00:00
Akash Levy 94bc6937d3
Merge branch 'YosysHQ:main' into main 2025-04-27 15:24:30 -07:00
George Rennie 70a44f035c tests: test opt_expr constant shift edge cases 2025-04-26 12:40:04 +02:00
KrystalDelusion 6564810ae3
Merge pull request #4992 from Anhijkt/fix-ice40dsp-unsigned 
ice40_dsp: fix const handling
 2025-04-26 11:15:02 +12:00
Akash Levy f67da2df2f
Merge branch 'YosysHQ:main' into main 2025-04-23 15:22:38 -07:00
Emil J. Tywoniak 9631f6ece5 liberty: fix tests 2025-04-23 20:20:43 +00:00
Mike Inouye bf8aece4e4 Add test to verify that the liberty format is properly parsed. 2025-04-23 18:40:35 +00:00
Akash Levy e9bf25f333 Undo flatten -scopeinfo to -noscopeinfo 2025-04-22 16:32:22 -07:00
Akash Levy 10ac596a51 Disable failing cutpoint_blackbox 2025-04-21 19:49:57 -07:00
Akash Levy 5f5ed1b29e Merge upstream yosys 2025-04-21 17:36:24 -07:00