mirror of https://github.com/YosysHQ/yosys.git
finalized tests
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williamzhu17
parent
39be4f29bd
commit
fc86bd8e74
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@ -20,22 +20,18 @@ equiv_opt -assert opt_balance_tree
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design -load postopt
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# Checks if inputs to and gates has been rewired
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select -set a_wires i:a %co
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select -set driven_by_a @a_wires %co
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select -set driven_by_a i:a %co %co
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select -set and_a_cell t:$and @driven_by_a %i
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select -set b_wires i:b %co
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select -set driven_by_b @b_wires %co
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select -set driven_by_b i:b %co %co
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select -set and_b_cell t:$and @driven_by_b %i
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select -assert-none @and_a_cell @and_b_cell %d
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select -set c_wires i:c %co
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select -set driven_by_c @c_wires %co
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select -set driven_by_c i:c %co %co
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select -set and_c_cell t:$and @driven_by_c %i
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select -set d_wires i:d %co
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select -set driven_by_d @d_wires %co
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select -set driven_by_d i:d %co %co
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select -set and_d_cell t:$and @driven_by_d %i
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select -assert-none @and_c_cell @and_d_cell %d
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@ -69,8 +65,7 @@ equiv_opt -assert opt_balance_tree
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design -load postopt
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# Checks if y is still wired up to the correct gate
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select -set y_wires o:y %ci
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select -set y_driver @y_wires %ci
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select -set y_driver o:y %ci %ci
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select -set and_y_cell t:$and @y_driver %i
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select @and_y_cell -assert-count 1
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select -set inputs @and_y_cell %ci
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@ -107,6 +102,13 @@ equiv_opt -assert opt_balance_tree
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design -load postopt
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select -assert-count 3 t:$and
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# Checks if temp is still wired up to the correct gate
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select -set temp_driver w:temp %ci %ci
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select -set and_cell t:$and @temp_driver %i
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select @and_cell -assert-count 1
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select -set inputs @and_cell %ci
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select -assert-count 1 @inputs i:c %i
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design -reset
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log -pop
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@ -134,6 +136,42 @@ equiv_opt -assert opt_balance_tree
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design -load postopt
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select -assert-count 3 t:$and
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# Checks if x[1] is still wired up to the correct gate
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select -set target_drivers o:x %ci %ci
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select -set target_cells t:$and @target_drivers %i
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select -set inputs @target_cells %ci
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select -assert-count 1 @inputs i:c %i
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design -reset
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log -pop
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log -header "Fanout going to multiple outputs"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire [2:0] x,
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output wire y
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);
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assign x[0] = a & b;
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assign x[1] = x[0] & c;
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assign x[2] = x[1] & d;
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assign y = x[1];
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_balance_tree
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equiv_opt -assert opt_balance_tree
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design -load postopt
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select -assert-count 3 t:$and
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design -reset
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log -pop
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@ -164,33 +202,12 @@ equiv_opt -assert opt_balance_tree
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design -load postopt
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select -assert-count 3 t:$and
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design -reset
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log -pop
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log -header "Fanout going to multiple of the same word"
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log -push
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design -reset
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read_verilog <<EOF
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module top (
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input wire a,
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input wire b,
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input wire c,
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input wire d,
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output wire [3:0] x
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);
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assign x[0] = a & b;
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assign x[1] = x[0] & c;
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assign x[2] = x[1] & d;
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assign x[3] = x[1];
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endmodule
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EOF
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check -assert
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# Check equivalence after opt_balance_tree
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equiv_opt -assert opt_balance_tree
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design -load postopt
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select -assert-count 3 t:$and
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# Checks if y is still wired up to the correct gate
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select -set y_wires o:y %ci
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select -set y_driver @y_wires %ci %ci
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select -set and_y_cell t:$and @y_driver %i
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select -set inputs @and_y_cell %ci
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select -assert-count 1 @inputs i:c %i
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design -reset
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log -pop
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@ -222,45 +239,37 @@ design -load postopt
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# Checks if inputs to and gates has been rewired
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# a and b
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select -set a_wires i:a %co
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select -set driven_by_a @a_wires %co
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select -set driven_by_a i:a %co %co
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select -set and_a_cell t:$and @driven_by_a %i
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select -set b_wires i:b %co
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select -set driven_by_b @b_wires %co
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select -set driven_by_b i:b %co %co
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select -set and_b_cell t:$and @driven_by_b %i
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select -assert-none @and_a_cell @and_b_cell %d
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# c and d
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select -set c_wires i:c %co
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select -set driven_by_c @c_wires %co
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select -set driven_by_c i:c %co %co
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select -set and_c_cell t:$and @driven_by_c %i
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select -set d_wires i:d %co
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select -set driven_by_d @d_wires %co
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select -set driven_by_d i:d %co %co
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select -set and_d_cell t:$and @driven_by_d %i
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select -assert-none @and_c_cell @and_d_cell %d
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# e and f
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select -set e_wires i:e %co
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select -set driven_by_e @e_wires %co
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select -set driven_by_e i:e %co %co
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select -set and_e_cell t:$and @driven_by_e %i
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select -set f_wires i:f %co
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select -set driven_by_f @f_wires %co
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select -set driven_by_f i:f %co %co
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select -set and_f_cell t:$and @driven_by_f %i
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select -assert-none @and_e_cell @and_f_cell %d
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# g and h
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select -set g_wires i:g %co
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select -set driven_by_g @g_wires %co
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select -set driven_by_g i:g %co %co
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select -set and_g_cell t:$and @driven_by_g %i
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select -set h_wires i:h %co
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select -set driven_by_h @h_wires %co
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select -set driven_by_h i:h %co %co
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select -set and_h_cell t:$and @driven_by_h %i
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select -assert-none @and_g_cell @and_h_cell %d
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