mirror of https://github.com/YosysHQ/yosys.git
Merge branch 'YosysHQ:main' into main
This commit is contained in:
Akash Levy
GitHub
commit
94bc6937d3
2
Makefile
2
Makefile
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@ -176,7 +176,7 @@ ifeq ($(OS), Haiku)
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CXXFLAGS += -D_DEFAULT_SOURCE
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endif
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YOSYS_VER := 0.52+102
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YOSYS_VER := 0.52+117
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YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
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YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
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YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
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@ -2410,7 +2410,12 @@ struct CxxrtlWorker {
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auto cell_attrs = scopeinfo_attributes(cell, ScopeinfoAttrs::Cell);
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cell_attrs.erase(ID::module_not_derived);
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f << indent << "scopes->add(path, " << escape_cxx_string(get_hdl_name(cell)) << ", ";
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f << escape_cxx_string(cell->get_string_attribute(ID(module))) << ", ";
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if (module_attrs.count(ID(hdlname))) {
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f << escape_cxx_string(module_attrs.at(ID(hdlname)).decode_string());
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} else {
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f << escape_cxx_string(cell->get_string_attribute(ID(module)));
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}
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f << ", ";
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dump_serialized_metadata(module_attrs);
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f << ", ";
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dump_serialized_metadata(cell_attrs);
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@ -1919,6 +1919,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
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if (!str.empty() && str[0] == '\\' && (template_node->type == AST_STRUCT || template_node->type == AST_UNION)) {
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// replace instance with wire representing the packed structure
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newNode = make_packed_struct(template_node, str, attributes);
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if (newNode->attributes.count(ID::wiretype))
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delete newNode->attributes[ID::wiretype];
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newNode->set_attribute(ID::wiretype, mkconst_str(resolved_type_node->str));
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// add original input/output attribute to resolved wire
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newNode->is_input = this->is_input;
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@ -34,7 +34,6 @@ ram block $__CC_BRAM_TDP_ {
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}
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portoption "WR_MODE" "WRITE_THROUGH" {
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rdwr new;
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wrtrans all new;
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}
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wrbe_separate;
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optional_rw;
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@ -48,7 +48,7 @@ module GP_COUNT14(input CLK, input wire RST, output reg OUT);
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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OUT <= (count == 14'h0);
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OUT = (count == 14'h0);
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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@ -133,10 +133,10 @@ module GP_COUNT14_ADV(input CLK, input RST, output reg OUT,
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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if(UP)
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OUT <= (count == 14'h3fff);
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OUT = (count == 14'h3fff);
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else
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OUT <= (count == 14'h0);
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POUT <= count[7:0];
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OUT = (count == 14'h0);
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POUT = count[7:0];
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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@ -272,10 +272,10 @@ module GP_COUNT8_ADV(input CLK, input RST, output reg OUT,
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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if(UP)
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OUT <= (count == 8'hff);
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OUT = (count == 8'hff);
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else
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OUT <= (count == 8'h0);
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POUT <= count;
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OUT = (count == 8'h0);
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POUT = count;
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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@ -413,8 +413,8 @@ module GP_COUNT8(
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//Combinatorially output underflow flag whenever we wrap low
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always @(*) begin
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OUT <= (count == 8'h0);
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POUT <= count;
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OUT = (count == 8'h0);
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POUT = count;
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end
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//POR or SYSRST reset value is COUNT_TO. Datasheet is unclear but conversations w/ Silego confirm.
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@ -488,23 +488,23 @@ module GP_DCMPMUX(input[1:0] SEL, input[7:0] IN0, input[7:0] IN1, input[7:0] IN2
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always @(*) begin
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case(SEL)
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2'd00: begin
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OUTA <= IN0;
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OUTB <= IN3;
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OUTA = IN0;
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OUTB = IN3;
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end
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2'd01: begin
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OUTA <= IN1;
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OUTB <= IN2;
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OUTA = IN1;
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OUTB = IN2;
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end
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2'd02: begin
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OUTA <= IN2;
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OUTB <= IN1;
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OUTA = IN2;
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OUTB = IN1;
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end
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2'd03: begin
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OUTA <= IN3;
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OUTB <= IN0;
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OUTA = IN3;
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OUTB = IN0;
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end
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endcase
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@ -635,7 +635,7 @@ module GP_DLATCH(input D, input nCLK, output reg Q);
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initial Q = INIT;
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always @(*) begin
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if(!nCLK)
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Q <= D;
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Q = D;
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end
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endmodule
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@ -644,7 +644,7 @@ module GP_DLATCHI(input D, input nCLK, output reg nQ);
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initial nQ = INIT;
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always @(*) begin
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if(!nCLK)
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nQ <= ~D;
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nQ = ~D;
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end
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endmodule
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@ -653,9 +653,9 @@ module GP_DLATCHR(input D, input nCLK, input nRST, output reg Q);
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initial Q = INIT;
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always @(*) begin
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if(!nRST)
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Q <= 1'b0;
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Q = 1'b0;
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else if(!nCLK)
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Q <= D;
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Q = D;
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end
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endmodule
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@ -664,9 +664,9 @@ module GP_DLATCHRI(input D, input nCLK, input nRST, output reg nQ);
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initial nQ = INIT;
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always @(*) begin
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if(!nRST)
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nQ <= 1'b1;
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nQ = 1'b1;
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else if(!nCLK)
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nQ <= ~D;
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nQ = ~D;
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end
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endmodule
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@ -675,9 +675,9 @@ module GP_DLATCHS(input D, input nCLK, input nSET, output reg Q);
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initial Q = INIT;
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always @(*) begin
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if(!nSET)
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Q <= 1'b1;
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Q = 1'b1;
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else if(!nCLK)
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Q <= D;
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Q = D;
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end
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endmodule
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@ -686,9 +686,9 @@ module GP_DLATCHSI(input D, input nCLK, input nSET, output reg nQ);
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initial nQ = INIT;
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always @(*) begin
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if(!nSET)
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nQ <= 1'b0;
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nQ = 1'b0;
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else if(!nCLK)
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nQ <= ~D;
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nQ = ~D;
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end
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endmodule
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@ -698,9 +698,9 @@ module GP_DLATCHSR(input D, input nCLK, input nSR, output reg Q);
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initial Q = INIT;
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always @(*) begin
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if(!nSR)
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Q <= SRMODE;
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Q = SRMODE;
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else if(!nCLK)
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Q <= D;
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Q = D;
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end
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endmodule
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@ -710,9 +710,9 @@ module GP_DLATCHSRI(input D, input nCLK, input nSR, output reg nQ);
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initial nQ = INIT;
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always @(*) begin
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if(!nSR)
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nQ <= ~SRMODE;
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nQ = ~SRMODE;
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else if(!nCLK)
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nQ <= ~D;
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nQ = ~D;
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end
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endmodule
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@ -23,7 +23,7 @@ match mul
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endmatch
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code sigA sigB sigH
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auto unextend = [](const SigSpec &sig) {
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auto unextend_signed = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != sig[i-1])
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@ -32,8 +32,16 @@ code sigA sigB sigH
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++i;
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return sig.extract(0, i);
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};
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sigA = unextend(port(mul, \A));
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sigB = unextend(port(mul, \B));
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auto unextend_unsigned = [](const SigSpec &sig) {
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int i;
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for (i = GetSize(sig)-1; i > 0; i--)
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if (sig[i] != SigBit(State::S0))
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break;
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++i;
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return sig.extract(0, i);
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};
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sigA = param(mul, \A_SIGNED).as_bool() ? unextend_signed(port(mul, \A)) : unextend_unsigned(port(mul, \A));
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sigB = param(mul, \B_SIGNED).as_bool() ? unextend_signed(port(mul, \B)) : unextend_unsigned(port(mul, \B));
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SigSpec O;
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if (mul->type == $mul)
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@ -0,0 +1,80 @@
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read_verilog << EOT
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module top(input wire [14:0] a, output wire [18:0] b);
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assign b = a*$unsigned(5'b01111);
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endmodule
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EOT
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prep
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ice40_dsp
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read_verilog << EOT
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module ref(a, b);
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wire _0_;
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wire _1_;
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wire _2_;
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wire [12:0] _3_;
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(* src = "<<EOT:1.30-1.31" *)
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input [14:0] a;
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wire [14:0] a;
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(* src = "<<EOT:1.52-1.53" *)
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output [18:0] b;
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wire [18:0] b;
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SB_MAC16 #(
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.A_REG(1'h0),
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.A_SIGNED(32'd0),
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.BOTADDSUB_CARRYSELECT(2'h0),
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.BOTADDSUB_LOWERINPUT(2'h2),
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.BOTADDSUB_UPPERINPUT(1'h1),
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.BOTOUTPUT_SELECT(2'h3),
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.BOT_8x8_MULT_REG(1'h0),
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.B_REG(1'h0),
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.B_SIGNED(32'd0),
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.C_REG(1'h0),
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.D_REG(1'h0),
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.MODE_8x8(1'h0),
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.NEG_TRIGGER(1'h0),
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.PIPELINE_16x16_MULT_REG1(1'h0),
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.PIPELINE_16x16_MULT_REG2(1'h0),
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.TOPADDSUB_CARRYSELECT(2'h3),
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.TOPADDSUB_LOWERINPUT(2'h2),
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.TOPADDSUB_UPPERINPUT(1'h1),
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.TOPOUTPUT_SELECT(2'h3),
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.TOP_8x8_MULT_REG(1'h0)
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) _4_ (
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.A({ 1'h0, a }),
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.ACCUMCI(1'hx),
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.ACCUMCO(_1_),
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.ADDSUBBOT(1'h0),
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.ADDSUBTOP(1'h0),
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.AHOLD(1'h0),
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.B(16'b1111),
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.BHOLD(1'h0),
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.C(16'h0000),
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.CE(1'h0),
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.CHOLD(1'h0),
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.CI(1'hx),
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.CLK(1'h0),
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.CO(_2_),
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.D(16'h0000),
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.DHOLD(1'h0),
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.IRSTBOT(1'h0),
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.IRSTTOP(1'h0),
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.O({ _3_, b }),
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.OHOLDBOT(1'h0),
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.OHOLDTOP(1'h0),
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.OLOADBOT(1'h0),
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.OLOADTOP(1'h0),
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.ORSTBOT(1'h0),
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.ORSTTOP(1'h0),
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.SIGNEXTIN(1'hx),
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.SIGNEXTOUT(_0_)
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);
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endmodule
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EOT
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techmap -wb -D EQUIV -autoproc -map +/ice40/cells_sim.v
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equiv_make top ref equiv
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select -assert-any -module equiv t:$equiv
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equiv_induct
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equiv_status -assert
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