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Merge branch 'main' into opt_balance_tree-tests

This commit is contained in:
williamzhu17 2025-05-11 09:07:17 -07:00
parent b265ea9dcf 3bcbfe4dde
commit e0714ca714
12 changed files with 270 additions and 254 deletions
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2
.github/workflows/codeql.yml vendored
View File

@ -31,7 +31,7 @@ jobs:
run: cd verific/tclmain && make -j6
- name: Build
run: make yosys -j6
run: make yosys -j6 ENABLE_CCACHE=0
- name: Perform CodeQL Analysis
uses: github/codeql-action/analyze@v3

6
Makefile
View File

@ -7,7 +7,7 @@ CONFIG := none
# CONFIG := msys2-64
# features (the more the better)
ENABLE_TCL := 0
ENABLE_TCL := 1
ENABLE_ABC := 1
ENABLE_GLOB := 1
ENABLE_PLUGINS := 0
@ -23,7 +23,7 @@ ENABLE_VERIFIC_SILIMATE_EXTENSIONS := 1
ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 0
ENABLE_VERIFIC_EDIF := 0
ENABLE_VERIFIC_LIBERTY := 0
ENABLE_VERIFIC_UPF := 1
ENABLE_VERIFIC_UPF := 0
ENABLE_COVER := 1
ENABLE_LIBYOSYS := 0
ENABLE_ZLIB := 1
@ -1280,4 +1280,4 @@ echo-cxx:
FORCE:
.PHONY: all top-all abc test install install-abc docs clean mrproper qtcreator coverage vcxsrc
.PHONY: config-clean config-clang config-gcc config-gcc-static config-gprof config-sudo wheel install_wheel
.PHONY: config-clean config-clang config-gcc config-gcc-static config-gprof config-sudo

36
frontends/verific/verific.cc
View File

@ -120,6 +120,8 @@ int verific_verbose;
bool verific_import_pending;
string verific_error_msg;
int verific_sva_fsm_limit;
bool verific_opt; // SILIMATE: enable Verific optimizations
bool verific_no_split_complex_ports; // SILIMATE: disable splitting of complex ports
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
vector<string> verific_incdirs, verific_libdirs, verific_libexts;
@ -3078,7 +3080,7 @@ void verific_cleanup()
verific_import_pending = false;
}
std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top, bool opt, bool no_split_complex_port)
std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top)
{
verific_sva_fsm_limit = 16;
@ -3120,7 +3122,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
if (!verific_error_msg.empty())
log_error("%s\n", verific_error_msg.c_str());
if (!no_split_complex_port)
if (!verific_no_split_complex_ports)
for (auto nl : nl_todo)
nl.second->ChangePortBusStructures(1 /* hierarchical */);
@ -3132,8 +3134,8 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
auto it = nl_todo.begin();
Netlist *nl = it->second;
// SILIMATE: use Verific optimization
if (opt) {
// SILIMATE: use Verific optimizations
if (verific_opt) {
log(" Optimizing netlist for %s.\n", it->first.c_str());
log(" Inferring clock enable muxes for %s.\n", it->first.c_str());
@ -3606,6 +3608,10 @@ struct VerificPass : public Pass {
verific_verbose = 0;
verific_sva_fsm_limit = 16;
// SILIMATE: added flags
verific_opt = false;
verific_no_split_complex_ports = false;
const char *release_str = Message::ReleaseString();
time_t release_time = Message::ReleaseDate();
char *release_tmstr = ctime(&release_time);
@ -3753,6 +3759,16 @@ struct VerificPass : public Pass {
}
#ifdef VERIFIC_SYSTEMVERILOG_SUPPORT
if (GetSize(args) > argidx && args[argidx] == "-optimization") {
verific_opt = true;
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-no_split_complex_ports") {
verific_no_split_complex_ports = true;
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-set_ignore_translate_off") {
veri_file::SetIgnoreTranslateOff(1);
goto check_error;
@ -3776,6 +3792,18 @@ struct VerificPass : public Pass {
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-set_relaxed_file_libext_modes") {
veri_file::AddLibExt(".v");
veri_file::AddLibExt(".vh");
veri_file::AddLibExt(".sv");
veri_file::AddLibExt(".sv1");
veri_file::AddLibExt(".svh");
veri_file::AddLibExt(".svp");
veri_file::AddLibExt(".h");
veri_file::AddLibExt(".inc");
goto check_error;
}
if (GetSize(args) > argidx && args[argidx] == "-ignore_module") {
for (argidx++; argidx < GetSize(args); argidx++) {
string name = args[argidx];

5
frontends/verific/verific.h
View File

@ -26,8 +26,11 @@ YOSYS_NAMESPACE_BEGIN
extern int verific_verbose;
extern bool verific_opt; // SILIMATE: enable Verific optimizations
extern bool verific_no_split_complex_ports; // SILIMATE: disable splitting of complex ports
extern bool verific_import_pending;
extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string(), bool opt = true, bool no_split_complex_ports = true);
extern std::string verific_import(Design *design, const std::map<std::string,std::string> &parameters, std::string top = std::string());
extern pool<int> verific_sva_prims;

2
kernel/log.h
View File

@ -148,7 +148,7 @@ static inline bool ys_debug(int n = 0) { if (log_force_debug) return true; log_d
#else
static inline bool ys_debug(int = 0) { return false; }
#endif
# define log_debug(...) do { if (ys_debug(1)) log(__VA_ARGS__); } while (0)
static inline void log_debug(const char *format, ...) { if (ys_debug(1)) { va_list args; va_start(args, format); logv(format, args); va_end(args); } }
static inline void log_suppressed() {
if (log_debug_suppressed && !log_make_debug) {

6
kernel/rtlil.cc
View File

@ -1254,6 +1254,12 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_modules(RTLIL::SelectPartial
return result;
}
void RTLIL::Design::run_pass(std::string command) {
log("\n-- Running command `%s' --\n", command.c_str());
Pass::call(this, command);
log_flush();
}
RTLIL::Module::Module()
{
static unsigned int hashidx_count = 123456789;

4
kernel/rtlil.h
View File

@ -1446,6 +1446,10 @@ struct RTLIL::Design
// returns all selected unboxed whole modules, warning the user if any
// partially selected or boxed modules have been ignored
std::vector<RTLIL::Module*> selected_unboxed_whole_modules_warn() const { return selected_modules(SELECT_WHOLE_WARN, SB_UNBOXED_WARN); }
// SILIMATE ADDED TO IMPROVE PYOSYS API
void run_pass(std::string command);
#ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
#endif

20
passes/hierarchy/hierarchy.cc
View File

@ -794,12 +794,6 @@ struct HierarchyPass : public Pass {
log(" -auto-top\n");
log(" automatically determine the top of the design hierarchy and mark it.\n");
log("\n");
log(" -opt\n");
log(" optimize all modules in design hierarchy.\n");
log("\n");
log(" -no_split_complex_ports\n");
log(" Complex ports (structs or arrays) are not split and remain packed as a single port.\n");
log("\n");
log(" -chparam name value \n");
log(" elaborate the top module using this parameter value. Modules on which\n");
log(" this parameter does not exist may cause a warning message to be output.\n");
@ -827,8 +821,6 @@ struct HierarchyPass : public Pass {
{
log_header(design, "Executing HIERARCHY pass (managing design hierarchy).\n");
bool flag_opt = false;
bool flag_no_split_complex_ports = false;
bool flag_check = false;
bool flag_simcheck = false;
bool flag_smtcheck = false;
@ -940,14 +932,6 @@ struct HierarchyPass : public Pass {
auto_top_mode = true;
continue;
}
if (args[argidx] == "-opt") {
flag_opt = true;
continue;
}
if (args[argidx] == "-no_split_complex_ports") {
flag_no_split_complex_ports = true;
continue;
}
if (args[argidx] == "-chparam" && argidx+2 < args.size()) {
const std::string &key = args[++argidx];
const std::string &value = args[++argidx];
@ -1002,7 +986,7 @@ struct HierarchyPass : public Pass {
if (top_mod == nullptr && !load_top_mod.empty()) {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending) {
load_top_mod = verific_import(design, parameters, load_top_mod, flag_opt, flag_no_split_complex_ports);
load_top_mod = verific_import(design, parameters, load_top_mod);
top_mod = design->module(RTLIL::escape_id(load_top_mod));
}
#endif
@ -1011,7 +995,7 @@ struct HierarchyPass : public Pass {
} else {
#ifdef YOSYS_ENABLE_VERIFIC
if (verific_import_pending)
verific_import(design, parameters, std::string(), flag_opt, flag_no_split_complex_ports);
verific_import(design, parameters, std::string());
#endif
}

4
passes/silimate/longloop_select.cc
View File

@ -234,13 +234,13 @@ struct LongLoopSelect : public ScriptPass {
}
}
if (!abc_script.empty()) {
std::string command = "recover_names abc -map_src " + src_info + " -script " + abc_script;
std::string command = "abc -map_src " + src_info + " -script " + abc_script;
log(" Executing: %s\n", command.c_str());
log_flush();
Pass::call(design, command);
} else if (!abc_options.empty()) {
abc_options.erase(std::remove(abc_options.begin(), abc_options.end(), '"'), abc_options.end());
std::string command = "recover_names abc -map_src " + src_info + " " + abc_options;
std::string command = "abc -map_src " + src_info + " " + abc_options;
log(" Executing: %s\n", command.c_str());
log_flush();
Pass::call(design, command);

290
passes/silimate/opt_balance_tree.cc
View File

@ -19,40 +19,35 @@
*
*/
#include "kernel/sigtools.h"
#include "kernel/yosys.h"
#include "kernel/sigtools.h"
USING_YOSYS_NAMESPACE
PRIVATE_NAMESPACE_BEGIN
struct OptBalanceTreeWorker {
// Module and signal map
Design *design;
Module *module;
SigMap sigmap;
bool allow_off_chain;
int limit = -1;
// Counts of each cell type that are getting balanced
dict<IdString, int> cell_count;
// Driver data
dict<SigBit, tuple<IdString, IdString, int>> bit_drivers_db;
// Load data
dict<SigBit, pool<tuple<IdString, IdString, int>>> bit_users_db;
// Cells to remove
pool<Cell*> remove_cells;
// Signal chain data structures
dict<SigSpec, Cell *> sig_chain_next;
dict<SigSpec, Cell *> sig_chain_prev;
dict<SigSpec, Cell*> sig_chain_next;
dict<SigSpec, Cell*> sig_chain_prev;
pool<SigBit> sigbit_with_non_chain_users;
pool<Cell *> chain_start_cells;
pool<Cell *> candidate_cells;
pool<Cell*> chain_start_cells;
pool<Cell*> candidate_cells;
// Ignore signals fanout while looking ahead which chains to split.
// Post splitfanout, take that into account.
void make_sig_chain_next_prev(IdString cell_type, bool ignore_split)
{
// Mark all wires with keep attribute as having non-chain users
void make_sig_chain_next_prev(IdString cell_type) {
// Mark all wires with keep attribute or output port as having non-chain users
for (auto wire : module->wires()) {
if (wire->get_bool_attribute(ID::keep)) {
if (wire->get_bool_attribute(ID::keep) || wire->port_output) {
for (auto bit : sigmap(wire))
sigbit_with_non_chain_users.insert(bit);
}
@ -66,40 +61,34 @@ struct OptBalanceTreeWorker {
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec b_sig = sigmap(cell->getPort(ID::B));
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
// If a_sig already has a chain user, mark its bits as having non-chain users
if (sig_chain_next.count(a_sig)) {
if (!ignore_split)
for (auto a_bit : a_sig.bits())
sigbit_with_non_chain_users.insert(a_bit);
// Otherwise, mark cell as the next in the chain relative to a_sig
} else {
if (fanout_in_range(y_sig)) {
sig_chain_next[a_sig] = cell;
}
// If a_sig already has a chain user, mark its bits as having non-chain users
if (sig_chain_next.count(a_sig))
for (auto a_bit : a_sig.bits())
sigbit_with_non_chain_users.insert(a_bit);
// Otherwise, mark cell as the next in the chain relative to a_sig
else {
sig_chain_next[a_sig] = cell;
}
if (!b_sig.empty()) {
// If b_sig already has a chain user, mark its bits as having non-chain users
if (sig_chain_next.count(b_sig)) {
if (!ignore_split)
for (auto b_bit : b_sig.bits())
sigbit_with_non_chain_users.insert(b_bit);
// Otherwise, mark cell as the next in the chain relative to b_sig
} else {
if (fanout_in_range(y_sig)) {
sig_chain_next[b_sig] = cell;
}
if (sig_chain_next.count(b_sig))
for (auto b_bit : b_sig.bits())
sigbit_with_non_chain_users.insert(b_bit);
// Otherwise, mark cell as the next in the chain relative to b_sig
else {
sig_chain_next[b_sig] = cell;
}
}
// Add cell as candidate
candidate_cells.insert(cell);
if (fanout_in_range(y_sig)) {
// Add cell as candidate
candidate_cells.insert(cell);
// Mark cell as the previous in the chain relative to y_sig
sig_chain_prev[y_sig] = cell;
}
// Mark cell as the previous in the chain relative to y_sig
sig_chain_prev[y_sig] = cell;
for (auto bit : y_sig.bits())
sig_chain_prev[bit] = cell;
}
// If cell is not matching type, mark all cell input signals as being non-chain users
else {
@ -111,8 +100,7 @@ struct OptBalanceTreeWorker {
}
}
void find_chain_start_cells()
{
void find_chain_start_cells() {
for (auto cell : candidate_cells) {
// Log candidate cell
log_debug("Considering %s (%s)\n", log_id(cell), log_id(cell->type));
@ -121,7 +109,7 @@ struct OptBalanceTreeWorker {
SigSpec a_sig = sigmap(cell->getPort(ID::A));
SigSpec b_sig = sigmap(cell->getPort(ID::B));
SigSpec prev_sig = sig_chain_prev.count(a_sig) ? a_sig : b_sig;
// This is a start cell if there was no previous cell in the chain for a_sig or b_sig
if (sig_chain_prev.count(a_sig) + sig_chain_prev.count(b_sig) != 1) {
chain_start_cells.insert(cell);
@ -137,10 +125,9 @@ struct OptBalanceTreeWorker {
}
}
vector<Cell *> create_chain(Cell *start_cell)
{
vector<Cell*> create_chain(Cell *start_cell) {
// Chain of cells
vector<Cell *> chain;
vector<Cell*> chain;
// Current cell
Cell *c = start_cell;
@ -163,8 +150,7 @@ struct OptBalanceTreeWorker {
return chain;
}
void wreduce(Cell *cell)
{
void wreduce(Cell *cell) {
// If cell is arithmetic, remove leading zeros from inputs, then clean up outputs
if (cell->type.in(ID($add), ID($mul))) {
// Remove leading zeros from inputs
@ -176,14 +162,13 @@ struct OptBalanceTreeWorker {
SigSpec inport_sig = sigmap(cell->getPort(inport));
cell->unsetPort(inport);
if (cell->getParam((inport == ID::A) ? ID::A_SIGNED : ID::B_SIGNED).as_bool()) {
while (GetSize(inport_sig) > 1 && inport_sig[GetSize(inport_sig) - 1] == State::S0 &&
inport_sig[GetSize(inport_sig) - 2] == State::S0) {
inport_sig.remove(GetSize(inport_sig) - 1, 1);
while (GetSize(inport_sig) > 1 && inport_sig[GetSize(inport_sig)-1] == State::S0 && inport_sig[GetSize(inport_sig)-2] == State::S0) {
inport_sig.remove(GetSize(inport_sig)-1, 1);
bits_removed++;
}
} else {
while (GetSize(inport_sig) > 0 && inport_sig[GetSize(inport_sig) - 1] == State::S0) {
inport_sig.remove(GetSize(inport_sig) - 1, 1);
while (GetSize(inport_sig) > 0 && inport_sig[GetSize(inport_sig)-1] == State::S0) {
inport_sig.remove(GetSize(inport_sig)-1, 1);
bits_removed++;
}
}
@ -203,8 +188,7 @@ struct OptBalanceTreeWorker {
width = std::max(cell->getParam(ID::A_WIDTH).as_int(), cell->getParam(ID::B_WIDTH).as_int()) + 1;
else if (cell->type == ID($mul))
width = cell->getParam(ID::A_WIDTH).as_int() + cell->getParam(ID::B_WIDTH).as_int();
else
log_abort();
else log_abort();
for (int i = GetSize(y_sig) - 1; i >= width; i--) {
module->connect(y_sig[i], State::S0);
y_sig.remove(i, 1);
@ -218,19 +202,18 @@ struct OptBalanceTreeWorker {
cell->fixup_parameters();
}
bool process_chain(vector<Cell *> &chain)
{
void process_chain(vector<Cell*> &chain) {
// If chain size is less than 3, no balancing needed
if (GetSize(chain) < 3)
return false;
return;
// Get mid, midnext (at index mid+1) and end of chain
Cell *mid_cell = chain[GetSize(chain) / 2];
Cell *cell = mid_cell; // SILIMATE: Set cell to mid_cell for better naming
Cell *midnext_cell = chain[GetSize(chain) / 2 + 1];
Cell *end_cell = chain.back();
log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n", GetSize(chain), log_id(mid_cell), log_id(midnext_cell),
log_id(end_cell));
log_debug("Balancing chain of %d cells: mid=%s, midnext=%s, endcell=%s\n",
GetSize(chain), log_id(mid_cell), log_id(midnext_cell), log_id(end_cell));
// Get mid signals
SigSpec mid_a_sig = sigmap(mid_cell->getPort(ID::A));
@ -259,17 +242,17 @@ struct OptBalanceTreeWorker {
sigmap.set(module);
// Get subtrees
vector<Cell *> left_chain(chain.begin(), chain.begin() + GetSize(chain) / 2);
vector<Cell *> right_chain(chain.begin() + GetSize(chain) / 2 + 1, chain.end());
vector<Cell*> left_chain(chain.begin(), chain.begin() + GetSize(chain) / 2);
vector<Cell*> right_chain(chain.begin() + GetSize(chain) / 2 + 1, chain.end());
// Recurse on subtrees
process_chain(left_chain);
process_chain(right_chain);
// Width reduce left subtree
for (auto c : left_chain)
wreduce(c);
// Width reduce right subtree
for (auto c : right_chain)
wreduce(c);
@ -279,15 +262,18 @@ struct OptBalanceTreeWorker {
// Width reduce mid cell
wreduce(mid_cell);
return true;
}
void cleanup()
{
void cleanup() {
// Remove cells
for (auto cell : remove_cells)
module->remove(cell);
// Fix ports
module->fixup_ports();
// Clear data structures
remove_cells.clear();
sig_chain_next.clear();
sig_chain_prev.clear();
sigbit_with_non_chain_users.clear();
@ -295,130 +281,17 @@ struct OptBalanceTreeWorker {
candidate_cells.clear();
}
bool fanout_in_range(SigSpec outsig)
{
// Check if output signal is "bit-split", skip if so
// This is a lookahead for the splitfanout pass that has this limitation
auto bit_users = bit_users_db[outsig[0]];
for (int i = 0; i < GetSize(outsig); i++) {
if (bit_users_db[outsig[i]] != bit_users) {
return false;
}
}
// Skip if fanout is above limit
if (limit != -1 && GetSize(bit_users) > limit) {
return false;
}
return true;
}
OptBalanceTreeWorker(Design *design, Module *module, const vector<IdString> cell_types, bool allow_off_chain, int limit)
: design(design), module(module), sigmap(module), allow_off_chain(allow_off_chain), limit(limit)
{
if (allow_off_chain) {
// Build bit_drivers_db
log("Building bit_drivers_db...\n");
for (auto cell : module->cells()) {
for (auto conn : cell->connections()) {
if (!cell->output(conn.first))
continue;
for (int i = 0; i < GetSize(conn.second); i++) {
SigBit bit(sigmap(conn.second[i]));
bit_drivers_db[bit] = tuple<IdString, IdString, int>(cell->name, conn.first, i);
}
}
}
// Build bit_users_db
log("Building bit_users_db...\n");
for (auto cell : module->cells()) {
for (auto conn : cell->connections()) {
if (!cell->input(conn.first))
continue;
for (int i = 0; i < GetSize(conn.second); i++) {
SigBit bit(sigmap(conn.second[i]));
if (!bit_drivers_db.count(bit))
continue;
bit_users_db[bit].insert(
tuple<IdString, IdString, int>(cell->name, conn.first, i - std::get<2>(bit_drivers_db[bit])));
}
}
}
// Build bit_users_db for output ports
log("Building bit_users_db for output ports...\n");
for (auto wire : module->wires()) {
if (!wire->port_output)
continue;
SigSpec sig(sigmap(wire));
for (int i = 0; i < GetSize(sig); i++) {
SigBit bit(sig[i]);
if (!bit_drivers_db.count(bit))
continue;
bit_users_db[bit].insert(
tuple<IdString, IdString, int>(wire->name, IdString(), i - std::get<2>(bit_drivers_db[bit])));
}
}
// Deselect all cells
Pass::call(design, "select -none");
// Do for each cell type
bool has_cell_to_split = false;
for (auto cell_type : cell_types) {
// Find chains of ops
make_sig_chain_next_prev(cell_type, true);
find_chain_start_cells();
// For each chain, if len >= 3, select all the elements
for (auto c : chain_start_cells) {
vector<Cell *> chain = create_chain(c);
if (GetSize(chain) < 3)
continue;
for (auto cell : chain) {
has_cell_to_split = true;
design->select(module, cell);
}
}
// Clean up
cleanup();
}
// Splitfanout of selected cells
if (has_cell_to_split)
Pass::call(design, "splitfanout");
// Reset selection for other passes
Pass::call(design, "select -clear");
// Recreate sigmap
sigmap.set(module);
}
OptBalanceTreeWorker(Module *module, const vector<IdString> cell_types) : module(module), sigmap(module) {
// Do for each cell type
for (auto cell_type : cell_types) {
// Find chains of ops
make_sig_chain_next_prev(cell_type, false);
make_sig_chain_next_prev(cell_type);
find_chain_start_cells();
// For each chain, if len >= 3, convert to tree via "rotation" and recurse on subtrees
for (auto c : chain_start_cells) {
vector<Cell *> chain = create_chain(c);
if (process_chain(chain)) {
// Rename cells and wires for formal check to pass as cells signals have changed functionalities post rotation
for (Cell *cell : chain) {
module->rename(cell, NEW_ID2_SUFFIX("rot_cell"));
}
for (Cell *cell : chain) {
SigSpec y_sig = sigmap(cell->getPort(ID::Y));
if (y_sig.is_wire()) {
Wire *wire = y_sig.as_wire();
if (wire && !wire->port_input && !wire->port_output) {
module->rename(y_sig.as_wire(), NEW_ID2_SUFFIX("rot_wire"));
}
}
}
}
vector<Cell*> chain = create_chain(c);
process_chain(chain);
cell_count[cell_type] += GetSize(chain);
}
@ -429,9 +302,8 @@ struct OptBalanceTreeWorker {
};
struct OptBalanceTreePass : public Pass {
OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$xnor/$add/$mul cascades to trees") {}
void help() override
{
OptBalanceTreePass() : Pass("opt_balance_tree", "$and/$or/$xor/$xnor/$add/$mul cascades to trees") { }
void help() override {
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
log("\n");
log(" opt_balance_tree [options] [selection]\n");
@ -439,47 +311,23 @@ struct OptBalanceTreePass : public Pass {
log("This pass converts cascaded chains of $and/$or/$xor/$xnor/$add/$mul cells into\n");
log("trees of cells to improve timing.\n");
log("\n");
log(" -allow-off-chain\n");
log(" Allows matching of cells that have loads outside the chain. These cells\n");
log(" will be replicated and balanced into a tree, but the original\n");
log(" cell will remain, driving its original loads.\n");
log(" -fanout_limit n\n");
log(" Max fanout to split.\n");
log(" -arith_only\n");
log(" Only balance arithmetic cells.\n");
log("\n");
}
void execute(std::vector<std::string> args, RTLIL::Design *design) override
{
void execute(std::vector<std::string> args, RTLIL::Design *design) override {
log_header(design, "Executing OPT_BALANCE_TREE pass (cell cascades to trees).\n");
bool allow_off_chain = false;
bool arith_only = false;
// Handle arguments
size_t argidx;
int limit = -1;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-allow-off-chain") {
allow_off_chain = true;
continue;
}
if (args[argidx] == "-fanout_limit" && argidx + 1 < args.size()) {
limit = std::stoi(args[++argidx]);
continue;
}
if (args[argidx] == "-arith_only") {
arith_only = true;
continue;
}
// No arguments yet
break;
}
extra_args(args, argidx, design);
// Count of all cells that were packed
dict<IdString, int> cell_count;
vector<IdString> cell_types = {ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul)};
if (arith_only) cell_types = {ID($add), ID($mul)};
const vector<IdString> cell_types = {ID($and), ID($or), ID($xor), ID($xnor), ID($add), ID($mul)};
for (auto module : design->selected_modules()) {
OptBalanceTreeWorker worker(design, module, cell_types, allow_off_chain, limit);
OptBalanceTreeWorker worker(module, cell_types);
for (auto cell : worker.cell_count) {
cell_count[cell.first] += cell.second;
}

147
tests/peepopt/muxorder.ys
View File

@ -1,5 +1,3 @@
log -header "Test basic s?(a+b):a pattern gets transformed (a,b module inputs)"
log -push
design -reset
@ -376,3 +374,148 @@ opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
log -pop
log -header "Test transform when widths are uneven with no intermediate values"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire [3:0] a;
input wire [2:0] b;
output wire [4:0] y;
input wire s;
assign y = s ? a + b : a;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$add %co1 %a w:y %i # assert adder rewired
log -pop
log -header "Test basic s ? (a * b) : a"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire [3:0] a;
input wire [3:0] b;
output wire [3:0] y;
input wire s;
assign y = s ? a * b : a;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$mul %co1 %a w:y %i # assert mult rewired
log -pop
log -header "Test basic s ? (a & b) : a"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire [3:0] a;
input wire [3:0] b;
output wire [3:0] y;
input wire s;
assign y = s ? a & b : a;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$and %co1 %a w:y %i # assert and rewired
log -pop
log -header "Test basic s ? (a | b) : a"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire a;
input wire b;
output wire y;
input wire s;
assign y = s ? a | b : a;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$or %co1 %a w:y %i # assert or rewired
log -pop
log -header "Test basic s ? (a ^ b) : a"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire [3:0] a;
input wire [3:0] b;
output wire [3:0] y;
input wire s;
assign y = s ? a ^ b : a;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$xor %co1 %a w:y %i # assert xor rewired
log -pop
log -header "Test basic s ? (a ~^ b) : a"
log -push
design -reset
read_verilog <<EOF
module top(a, b, s, y);
input wire [3:0] a;
input wire [3:0] b;
output wire [3:0] y;
input wire s;
assign y = s ? a ~^ b : a;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$xnor %co1 %a w:y %i # assert xnor rewired
log -pop
log -header "Nested conditionals"
log -push
design -reset
read_verilog <<EOF
module top(a, b, c, s0, s1, y);
input wire [3:0] a;
input wire [3:0] b;
input wire [3:0] c;
output wire [3:0] y;
input wire s0, s1;
wire [3:0] inter;
assign inter = s0 ? a + b : a;
assign y = s1 ? inter + c : inter;
endmodule
EOF
check -assert
wreduce
opt_clean
equiv_opt -assert peepopt -muxorder
design -load postopt
select -assert-any t:$add %co1 %a w:y %i # assert adder rewired

2
verific

@ -1 +1 @@
Subproject commit 3992c3755bec1ec68c6889509e33f6607873813f
Subproject commit 736d26da64484244def74ca9ac33acbeeb22185f