Merge branch 'YosysHQ:main' into main

Makefile

@@ -176,7 +176,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.53+39
+YOSYS_VER := 0.53+60
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)

backends/verilog/verilog_backend.cc

@@ -399,6 +399,7 @@ void dump_attributes(std::ostream &f, std::string indent, dict<RTLIL::IdString,
 	if (attr2comment)
 		as_comment = true;
 	for (auto it = attributes.begin(); it != attributes.end(); ++it) {
+		if (it->first == ID::single_bit_vector) continue;
 		if (it->first == ID::init && regattr) continue;
 		if (srcattronly && it->first != ID::src) continue;
 		f << stringf("%s" "%s %s", indent.c_str(), as_comment ? "/*" : "(*", id(it->first).c_str());
@@ -436,6 +437,9 @@ void dump_wire(std::ostream &f, std::string indent, RTLIL::Wire *wire)
 			range = stringf(" [%d:%d]", wire->start_offset, wire->width - 1 + wire->start_offset);
 		else
 			range = stringf(" [%d:%d]", wire->width - 1 + wire->start_offset, wire->start_offset);
+	} else {
+		if (wire->attributes.count(ID::single_bit_vector))
+			range = stringf(" [%d:%d]", wire->start_offset, wire->start_offset);
 	}
 	if (wire->port_input && !wire->port_output)
 		f << stringf("%s" "input%s %s;\n", indent.c_str(), range.c_str(), id(wire->name).c_str());

frontends/ast/genrtlil.cc

@@ -1446,6 +1446,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			wire->port_input = is_input;
 			wire->port_output = is_output;
 			wire->upto = range_swapped;
+
 			wire->is_signed = is_signed;
 
 			for (auto &attr : attributes) {

frontends/ast/simplify.cc

@@ -2086,6 +2086,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 					std::swap(range_left, range_right);
 					range_swapped = force_upto;
 				}
+				if (range_left == range_right)
+					set_attribute(ID::single_bit_vector, mkconst_int(1, false));
 			}
 		} else {
 			if (!range_valid)
@@ -2094,6 +2096,10 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 			range_swapped = false;
 			range_left = 0;
 			range_right = 0;
+			if (attributes.count(ID::single_bit_vector)) {
+				delete attributes[ID::single_bit_vector];
+				attributes.erase(ID::single_bit_vector);
+			}
 		}
 	}
 

frontends/verific/verific.cc

@@ -1629,6 +1629,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 		wire->start_offset = min(portbus->LeftIndex(), portbus->RightIndex());
 		wire->upto = portbus->IsUp();
 		import_attributes(wire->attributes, portbus, nl, portbus->Size());
+		if (portbus->Size() == 1)
+			wire->set_bool_attribute(ID::single_bit_vector);
 		SetIter si ;
 		Port *port ;
 		FOREACH_PORT_OF_PORTBUS(portbus, si, port) {
@@ -1826,6 +1828,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
 				break;
 			}
 			import_attributes(wire->attributes, netbus, nl, netbus->Size());
+			if (netbus->Size() == 1)
+				wire->set_bool_attribute(ID::single_bit_vector);
 
 			RTLIL::Const initval = Const(State::Sx, GetSize(wire));
 			bool initval_valid = false;

kernel/constids.inc

@@ -184,6 +184,7 @@ X(romstyle)
 X(S)
 X(SET)
 X(SET_POLARITY)
+X(single_bit_vector)
 X(SIZE)
 X(SRC)
 X(src)

passes/cmds/logger.cc

@@ -67,7 +67,7 @@ struct LoggerPass : public Pass {
 		log("    -check-expected\n");
 		log("        verifies that the patterns previously set up by -expect have actually\n");
 		log("        been met, then clears the expected log list.  If this is not called\n");
-		log("        manually, the check will happen at yosys exist time instead.\n");
+		log("        manually, the check will happen at yosys exit time instead.\n");
 		log("\n");
 	}
 

passes/techmap/libcache.cc

@@ -47,6 +47,13 @@
 		log("\n");
 		log("Displays the current cache settings and cached paths.\n");
 		log("\n");
+		log("    libcache {-verbose|-quiet}\n");
+		log("\n");
+		log("Controls cache use logging.\n");
+		log("\n");
+		log("    -verbose   Enable printing info when cache is used\n");
+		log("    -quiet     Disable printing info when cache is used (default)\n");
+		log("\n");
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *) override
 	{
@@ -55,6 +62,8 @@
 		bool purge = false;
 		bool all = false;
 		bool list = false;
+		bool verbose = false;
+		bool quiet = false;
 		std::vector<std::string> paths;
 
 		size_t argidx;
@@ -79,16 +88,24 @@
 				list = true;
 				continue;
 			}
+			if (args[argidx] == "-verbose") {
+				verbose = true;
+				continue;
+			}
+			if (args[argidx] == "-quiet") {
+				quiet = true;
+				continue;
+			}
 			std::string fname = args[argidx];
 			rewrite_filename(fname);
 			paths.push_back(fname);
 			break;
 		}
-		int modes = enable + disable + purge + list;
+		int modes = enable + disable + purge + list + verbose + quiet;
 		if (modes == 0)
-			log_cmd_error("At least one of -enable, -disable, -purge or -list is required.\n");
+			log_cmd_error("At least one of -enable, -disable, -purge, -list,\n-verbose, or -quiet is required.\n");
 		if (modes > 1)
-			log_cmd_error("Only one of -enable, -disable, -purge or -list may be present.\n");
+			log_cmd_error("Only one of -enable, -disable, -purge, -list,\n-verbose, or -quiet may be present.\n");
 
 		if (all && !paths.empty())
 			log_cmd_error("The -all option cannot be combined with a list of paths.\n");
@@ -121,6 +138,10 @@
 					LibertyAstCache::instance.cache_path.erase(path);
 				}
 			}
+		} else if (verbose) {
+			LibertyAstCache::instance.verbose = true;
+		} else if (quiet) {
+			LibertyAstCache::instance.verbose = false;
 		} else {
 			log_assert(false);
 		}

passes/techmap/libparse.cc

@@ -41,7 +41,8 @@ std::shared_ptr<const LibertyAst> LibertyAstCache::cached_ast(const std::string
 	auto it = cached.find(fname);
 	if (it == cached.end())
 		return nullptr;
-	log("Using cached data for liberty file `%s'\n", fname.c_str());
+	if (verbose)
+		log("Using cached data for liberty file `%s'\n", fname.c_str());
 	return it->second;
 }
 
@@ -51,7 +52,8 @@ void LibertyAstCache::parsed_ast(const std::string &fname, const std::shared_ptr
 	bool should_cache = it == cache_path.end() ? cache_by_default : it->second;
 	if (!should_cache)
 		return;
-	log("Caching data for liberty file `%s'\n", fname.c_str());
+	if (verbose)
+		log("Caching data for liberty file `%s'\n", fname.c_str());
 	cached.emplace(fname, ast);
 }
 

passes/techmap/libparse.h

@@ -140,6 +140,7 @@ namespace Yosys
 		dict<std::string, std::shared_ptr<const LibertyAst>> cached;
 
 		bool cache_by_default = false;
+		bool verbose = false;
 		dict<std::string, bool> cache_path;
 
 		std::shared_ptr<const LibertyAst> cached_ast(const std::string &fname);

tests/liberty/libcache.ys

@@ -1,3 +1,4 @@
+libcache -verbose
 libcache -enable busdef.lib
 
 logger -expect log "Caching is disabled by default." 1
@@ -14,8 +15,8 @@ logger -expect log "Caching data" 1
 read_liberty -lib busdef.lib; design -reset
 logger -check-expected
 
-logger -expect log "Using caching data" 1
-log Using caching data
+logger -expect log "Using cached data" 1
+log Using cached data
 read_liberty normal.lib; design -reset
 logger -check-expected
 
@@ -23,6 +24,13 @@ logger -expect log "Using cached data" 1
 read_liberty -lib busdef.lib; design -reset
 logger -check-expected
 
+libcache -quiet
+logger -expect log "Using cached data" 1
+log Using cached data
+read_liberty -lib busdef.lib; design -reset
+logger -check-expected
+libcache -verbose
+
 libcache -purge busdef.lib
 
 logger -expect log "Caching is disabled by default." 1

tests/verilog/sbvector.ys

@@ -0,0 +1,30 @@
+read_verilog <<EOT
+module foo(
+	output o,
+	input [0:0] i1,
+	input i2
+);
+    wire [0:0] w1 = i1 ^ i2;
+    wire w2 = ~i1;
+	assign o = w1 ^ w2;
+endmodule
+EOT
+
+hierarchy
+proc
+select -assert-count 1 w:i1
+select -assert-count 1 w:i1 a:single_bit_vector %i
+select -assert-count 1 w:i2
+select -assert-count 0 w:i2 a:single_bit_vector %i
+select -assert-count 1 w:w1
+select -assert-count 1 w:w1 a:single_bit_vector %i
+select -assert-count 1 w:w2
+select -assert-count 0 w:w2 a:single_bit_vector %i
+
+write_verilog verilog_sbvector.out
+!grep -qF 'wire [0:0] i1;' verilog_sbvector.out
+!grep -qF 'input [0:0] i1;' verilog_sbvector.out
+!grep -qF 'wire i2;' verilog_sbvector.out
+!grep -qF 'input i2;' verilog_sbvector.out
+!grep -qF 'wire [0:0] w1;' verilog_sbvector.out
+!grep -qF 'wire w2;' verilog_sbvector.out