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18229 Commits

Author SHA1 Message Date
Akash Levy 2f76595b16
Merge pull request #136 from Silimate/remove_filter_non_trigger_outputs 
Remove filter non trigger outputs
 2026-03-31 16:48:04 -07:00
AdvaySingh1 60d5e40897 Merge branch 'main' into remove_filter_non_trigger_outputs 2026-03-31 10:13:06 -07:00
AdvaySingh1 aea16d3888 Removed -filter_non_trigger_outputs functionality 2026-03-31 10:12:21 -07:00
Akash Levy b2e7c10bb7
Merge pull request #134 from Silimate/negopt_runtime_fix 
[ENG-1692] negopt runtime fix + small cleanup
 2026-03-30 17:32:13 -07:00
Akash Levy db1e0701b0
Apply suggestions from code review 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-03-30 17:31:59 -07:00
Akash Levy ed1d2e7e1e
Merge pull request #135 from Silimate/reg-rename 
Edge case handling in reg_rename
 2026-03-30 17:30:58 -07:00
Stan Lee 87e959d14c add warning message 2026-03-30 16:34:20 -07:00
Abhinav Tondapu df43a3097a [ENG-1692] negopt runtime fix + small cleanup 2026-03-30 16:30:46 -07:00
Akash Levy 5e7e172570
Merge pull request #133 from Silimate/sim 
Better support for arrays in RTL + VCD
 2026-03-30 15:12:11 -07:00
Stan Lee c767d90f3d add warning 2026-03-30 14:13:43 -07:00
Stan Lee e10f545c69 fixes 2026-03-30 13:13:14 -07:00
Stan Lee 857f356f1f remove ambiguity in implementation 2026-03-30 12:26:44 -07:00
Stan Lee 01f0fd751f fixes for arrays 2026-03-30 12:13:50 -07:00
Akash Levy 3ea2b222ab
Merge pull request #131 from Silimate/miter_opt_sat 
Miter opt sat
 2026-03-27 18:08:26 -07:00
Akash Levy f810bff900
Merge pull request #132 from Silimate/ignore_placeholder_ports 
[ENG-1827] ignore placeholder/empty ports from verific
 2026-03-27 16:41:20 -07:00
AdvaySingh1 8aebec79a8 Added -filter_non_trigger_outputs knob 2026-03-27 15:41:44 -07:00
Abhinav Tondapu d5122ed2fa [ENG-1827] ignore placeholder/empty ports from verific 2026-03-27 15:20:12 -07:00
AdvaySingh1 ad6546b05e Revert "Update passes/techmap/abc.cc" 
This reverts commit 20cf9fb461.
 2026-03-27 14:53:38 -07:00
Advay Singh 20cf9fb461
Update passes/techmap/abc.cc 
Co-authored-by: greptile-apps[bot] <165735046+greptile-apps[bot]@users.noreply.github.com>
 2026-03-27 12:45:57 -07:00
AdvaySingh1 5c94a47298 moved verific to main head 2026-03-26 17:02:57 -07:00
AdvaySingh1 113b3e02ce Removed adding struct partition object file 2026-03-26 16:59:58 -07:00
AdvaySingh1 972e4780c9 Removed extra struct partition pass 2026-03-26 16:58:09 -07:00
AdvaySingh1 f523760b75 merged with main 2026-03-26 16:50:59 -07:00
AdvaySingh1 f42a63941c Added initial clkmerge pass for multiple clock domains 2026-03-26 16:42:27 -07:00
Akash Levy 5376dc27e1 Update Verific for bugfix 2026-03-25 22:49:17 -07:00
Akash Levy 22bfdc23a8
Merge pull request #128 from Silimate/negopt_debug_logs 
adding temp debug logs to fix runtime issue
 2026-03-25 19:07:10 -07:00
Abhinav Tondapu 510ef01b09 adding temp debug logs to fix runtime issue 2026-03-25 16:55:29 -07:00
AdvaySingh1 f84fd46a17 Added test cases for clkmerge and cone_partition passes 2026-03-25 15:06:58 -07:00
AdvaySingh1 92e659f42a Added new port outputs anding the clock domain. TODO: fix if they belong to the same one and there's multiple 2026-03-24 20:00:24 -07:00
AdvaySingh1 f7a9af5252 Make the signal_map flag optional 2026-03-24 14:39:21 -07:00
Akash Levy d99ba91fe7
Merge pull request #126 from Silimate/fix_mem_crash 
Safe parameter extraction in mem_from_cell
 2026-03-23 07:39:16 -04:00
Akash Levy 0ed1f1bfa4 Smallfixes 2026-03-23 03:51:49 -07:00
Akash Levy 91739e79cb Safe parameter extraction in mem_from_cell 2026-03-23 03:30:55 -07:00
AdvaySingh1 b9ba2c3552 Checked out abc to the yosys-experimental branch 2026-03-20 15:05:03 -07:00
AdvaySingh1 f9f31afcb4 Makefile pass changes 2026-03-20 12:42:51 -07:00
AdvaySingh1 2fc0591b2c Added clkmerge pass 2026-03-20 12:42:24 -07:00
AdvaySingh1 e2a641f5a8 Added support for printing the cdc map file 2026-03-20 11:32:06 -07:00
AdvaySingh1 59dd03973e Added printing differnt clock domains in signal map 2026-03-20 10:37:47 -07:00
AdvaySingh1 daf5108434 Added inital cone_parition.cc pass. TODO: check with larger designs 2026-03-19 16:30:11 -07:00
AdvaySingh1 1711da5506 Moved the struct_partition pass to Silimate 2026-03-19 15:06:50 -07:00
AdvaySingh1 522ead01df Added small fixes 2026-03-19 15:04:13 -07:00
Akash Levy fc320a7e8e
Merge pull request #123 from Silimate/accessor_helpers 
adding more fast Cell accessors and small refactoring to reduce code dup
 2026-03-19 17:40:18 -04:00
AdvaySingh1 8536ab69c1 Added -o option for output file in struct_partition 2026-03-19 10:09:11 -07:00
AdvaySingh1 26db947b57 Added zinit 2026-03-19 10:08:52 -07:00
Akash Levy 7771a489e8
Merge pull request #124 from Silimate/sim 
Add debugging code before assertion
 2026-03-19 12:45:49 -04:00
AdvaySingh1 52fad78b40 Removed is_port for non-trigger outputs. TODO: add a flag which does this so POs are only those ones 2026-03-19 09:23:12 -07:00
AdvaySingh1 dc73249d8f Added support for printing the signal map 2026-03-18 16:23:41 -07:00
Stan Lee 8268a79af5 debug before assertion 2026-03-18 14:06:18 -07:00
AdvaySingh1 a3ffc5da30 Added new passes/sat/struct_partition.cc pass to propagate the ports out 2026-03-18 11:53:47 -07:00
Stan Lee f9d099503a Merge branch 'main' of github.com:silimate/yosys into sim 2026-03-17 11:44:18 -07:00