mirror of https://github.com/YosysHQ/yosys.git
Added initial clkmerge pass for multiple clock domains
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AdvaySingh1
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5376dc27e1
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f42a63941c
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2026 Silimate Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/ff.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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struct ClkMergePass : public Pass {
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ClkMergePass() : Pass("clkmerge", "merge multiple clock domains into one") { }
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void help() override
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" clkmerge [-target <signal>] [selection]\n");
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log("\n");
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log("This command rewrites all flip-flop clock ports in the selected modules to\n");
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log("use a single clock signal, effectively merging all clock domains into one.\n");
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log("\n");
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log("This is useful for miter-based equivalence checking where gold and gate\n");
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log("copies may use different clock signal names for what is logically the same\n");
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log("clock. Without merging, ABC's -dff mode will partition them into separate\n");
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log("clock domains, creating spurious cross-domain ports that degrade SAT\n");
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log("performance.\n");
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log("\n");
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log(" -target <signal>\n");
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log(" use the specified signal as the merged clock. if not given, the\n");
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log(" clock signal of the first FF encountered is used.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) override
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{
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std::string target_clk_name;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++) {
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if (args[argidx] == "-target" && argidx + 1 < args.size()) {
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target_clk_name = args[++argidx];
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continue;
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}
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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{
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SigMap sigmap(module);
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dict<SigBit, int> clk_domain_count;
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std::vector<std::pair<Cell*, SigSpec>> ff_clk_pairs;
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for (auto cell : module->selected_cells())
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{
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if (!cell->is_builtin_ff())
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continue;
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FfData ff(nullptr, cell);
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if (!ff.has_clk)
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continue;
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SigSpec clk = sigmap(ff.sig_clk);
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ff_clk_pairs.push_back({cell, clk});
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for (auto bit : clk)
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clk_domain_count[bit]++;
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}
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if (ff_clk_pairs.empty())
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continue;
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// Determine target clock
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SigSpec target_clk;
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if (!target_clk_name.empty()) {
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RTLIL::SigSpec sig;
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if (!SigSpec::parse_sel(sig, design, module, target_clk_name))
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log_cmd_error("Failed to parse target clock expression '%s'.\n", target_clk_name.c_str());
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target_clk = sigmap(sig);
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} else {
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target_clk = ff_clk_pairs[0].second;
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}
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// Collect distinct clocks
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pool<SigSpec> all_clks;
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for (auto &pair : ff_clk_pairs)
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all_clks.insert(pair.second);
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if (all_clks.size() <= 1) {
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log("Module %s: only one clock domain found, nothing to merge.\n", log_id(module));
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continue;
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}
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log("Module %s: merging %d clock domains into %s\n",
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log_id(module), GetSize(all_clks), log_signal(target_clk));
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int rewritten = 0;
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for (auto &pair : ff_clk_pairs)
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{
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Cell *cell = pair.first;
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SigSpec old_clk = pair.second;
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if (old_clk == target_clk)
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continue;
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// Fine-grain cells use ID::C, coarse-grain use ID::CLK
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if (cell->hasPort(ID::C))
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cell->setPort(ID::C, target_clk);
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else if (cell->hasPort(ID::CLK))
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cell->setPort(ID::CLK, target_clk);
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rewritten++;
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}
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log(" Rewrote clock on %d flip-flops.\n", rewritten);
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}
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}
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} ClkMergePass;
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PRIVATE_NAMESPACE_END
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