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[ENG-1827] ignore placeholder/empty ports from verific

This commit is contained in:
Abhinav Tondapu 2026-03-27 15:20:12 -07:00
parent 5376dc27e1
commit d5122ed2fa
1 changed files with 12 additions and 0 deletions
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12
frontends/verific/verific.cc
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@ -1593,6 +1593,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
Instance *inst;
PortRef *pr;
Att *attr;
pool<Net*> empty_port_nets;
FOREACH_ATTRIBUTE(nl, mi, attr) {
if (!strcmp(attr->Key(), "noblackbox"))
@ -1604,6 +1605,12 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
if (port->Bus())
continue;
if (port->GetAtt(" empty_port")) {
if (port->GetNet())
empty_port_nets.insert(port->GetNet());
continue;
}
if (verific_verbose)
log(" importing port %s.\n", port->Name());
@ -1687,6 +1694,9 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
FOREACH_NET_OF_NETLIST(nl, mi, net)
{
if (empty_port_nets.count(net))
continue;
if (net->IsRamNet())
{
RTLIL::Memory *memory = new RTLIL::Memory;
@ -2291,6 +2301,8 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
}
FOREACH_PORTREF_OF_INST(inst, mi2, pr) {
if (pr->GetPort()->GetAtt(" empty_port"))
continue;
if (verific_verbose)
log(" .%s(%s)\n", pr->GetPort()->Name(), pr->GetNet()->Name());
const char *port_name = pr->GetPort()->Name();