Merge pull request #128 from Silimate/negopt_debug_logs

adding temp debug logs to fix runtime issue
This commit is contained in:
Akash Levy 2026-03-25 19:07:10 -07:00 committed by GitHub
commit 22bfdc23a8
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GPG Key ID: B5690EEEBB952194
9 changed files with 55 additions and 22 deletions

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@ -60,8 +60,6 @@ struct NegoptPass : public Pass {
bool run_pre = false;
bool run_post = false;
log_header(design, "Executing NEGOPT pass (optimize negation patterns).\n");
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-pre") {
@ -76,28 +74,48 @@ struct NegoptPass : public Pass {
}
extra_args(args, argidx, design);
if (!run_pre && !run_post) {
run_pre = true;
run_post = true;
}
if (run_pre == run_post)
log_cmd_error("NEGOPT requires exactly one of -pre or -post.\n");
log_header(design, "Executing NEGOPT %s pass (optimize negation patterns).\n",
run_pre ? "PRE" : "POST");
constexpr int max_iterations = 100;
for (auto module : design->selected_modules()) {
auto log_module_event = [&](const char *event) {
log("%s %s\n", event, log_id(module));
log_flush();
};
auto log_pass_event = [&](const char *event, const char *pass_name, int iter = -1) {
if (iter >= 0)
log(" %s %s pass (iter=%d)\n", event, pass_name, iter + 1);
else
log(" %s %s pass\n", event, pass_name);
log_flush();
};
if (run_pre) {
log_module_event("Processing Module:");
// manual2sub and sub2neg only need to run once: no downstream
// pre-subpass creates the patterns they match
// separate pm instances so sub2neg sees the $sub cells manual2sub creates.
{
peepopt_pm pm(module);
pm.setup(module->selected_cells());
log_pass_event("Starting", "manual2sub");
pm.run_manual2sub();
log_pass_event("Ending", "manual2sub");
log_flush();
}
{
peepopt_pm pm(module);
pm.setup(module->selected_cells());
log_pass_event("Starting", "sub2neg");
pm.run_sub2neg();
log_pass_event("Ending", "sub2neg");
log_flush();
}
@ -108,33 +126,51 @@ struct NegoptPass : public Pass {
peepopt_pm pm(module);
pm.setup(module->selected_cells());
log_pass_event("Starting", "negexpand", iter);
pm.run_negexpand();
log_pass_event("Ending", "negexpand", iter);
log_flush();
log_pass_event("Starting", "negneg", iter);
pm.run_negneg();
log_pass_event("Ending", "negneg", iter);
log_flush();
log_pass_event("Starting", "negmux", iter);
pm.run_negmux();
log_pass_event("Ending", "negmux", iter);
log_flush();
}
if (did_something)
log_warning("NEGOPT pre reached max iterations (%d) in module %s without convergence.\n", max_iterations, log_id(module));
log_module_event("Finished Module:");
}
if (run_post) {
log_module_event("Processing Module:");
did_something = true;
for (int iter = 0; iter < max_iterations && did_something; iter++) {
did_something = false;
peepopt_pm pm(module);
pm.setup(module->selected_cells());
log_pass_event("Starting", "negrebuild", iter);
pm.run_negrebuild();
log_pass_event("Ending", "negrebuild", iter);
log_flush();
log_pass_event("Starting", "muxneg", iter);
pm.run_muxneg();
log_pass_event("Ending", "muxneg", iter);
log_flush();
log_pass_event("Starting", "neg2sub", iter);
pm.run_neg2sub();
log_pass_event("Ending", "neg2sub", iter);
log_flush();
}
if (did_something)
log_warning("NEGOPT post reached max iterations (%d) in module %s without convergence.\n", max_iterations, log_id(module));
log_module_event("Finished Module:");
}
}
}

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@ -94,7 +94,7 @@ code root_add inner_add_A not_gate_A subtrahend minuend result_sig is_signed
subtrahend = port(not_gate_A, \A);
log("manual2sub in %s: Found (a + ~b) + 1 pattern, creating $sub for %s\n", log_id(module), log_signal(result_sig));
log(" creating $sub for %s from (a + ~b) + 1\n", log_signal(result_sig));
Cell *cell = root_add;
int width = GetSize(result_sig);
int inner_width = GetSize(inner_y);
@ -196,7 +196,7 @@ code root_add inner_add_B not_gate_B minuend subtrahend result_sig is_signed
else
minuend = root_a;
log("manual2sub in %s: Found a + (~b + 1) pattern, creating $sub for %s\n", log_id(module), log_signal(result_sig));
log(" creating $sub for %s from a + (~b + 1)\n", log_signal(result_sig));
Cell *cell = root_add;
int width = GetSize(result_sig);
int inner_width = GetSize(inner_add_B->getPort(ID::Y));

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@ -60,8 +60,8 @@ code mux_a mux_b mux_s mux_y neg_a_in neg_a_y neg_b_in neg_b_y neg_a_signed neg_
neg_out_rs.extend_u0(GetSize(mux_y), neg_a_signed);
module->connect(mux_y, neg_out_rs);
log("muxneg pattern in %s: mux=%s, neg_a=%s, neg_b=%s\n",
log_id(module), log_id(mux), log_id(neg_a), log_id(neg_b));
log(" mux=%s, neg_a=%s, neg_b=%s\n",
log_id(mux), log_id(neg_a), log_id(neg_b));
new_mux->fixup_parameters();
new_neg->fixup_parameters();

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@ -62,8 +62,8 @@ code add_a add_b add_y neg_a neg_y neg_on_a add_a_signed add_b_signed neg_signed
add->setPort(\Y, add_y);
add->type = $sub;
log("neg2sub pattern in %s: add=%s, neg=%s (safe sub replacement)\n",
log_id(module), log_id(add), log_id(neg));
log(" add=%s, neg=%s (safe sub replacement)\n",
log_id(add), log_id(neg));
add->fixup_parameters();
autoremove(neg);

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@ -49,8 +49,7 @@ code neg_a neg_y add_a add_b a_signed
Cell *new_add = module->addAdd(NEW_ID2_SUFFIX("add"), neg_add_a, neg_add_b, neg_y, a_signed);
log("negexpand pattern in %s: neg=%s, add=%s\n",
log_id(module), log_id(neg), log_id(add));
log(" neg=%s, add=%s\n", log_id(neg), log_id(add));
neg_a_cell->fixup_parameters();
neg_b_cell->fixup_parameters();

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@ -60,8 +60,7 @@ code neg_a neg_y mux_a mux_b mux_s mux_y a_signed
Cell *new_mux = module->addMux(NEW_ID2_SUFFIX("mux"), neg_mux_a, neg_mux_b, mux_s, neg_y);
log("negmux pattern in %s: neg=%s, mux=%s\n",
log_id(module), log_id(neg), log_id(mux));
log(" neg=%s, mux=%s\n", log_id(neg), log_id(mux));
neg_a_cell->fixup_parameters();
neg_b_cell->fixup_parameters();

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@ -29,8 +29,7 @@ code neg1_a neg1_y neg2_a
module->connect(neg1_y, neg2_a);
log("negneg pattern in %s: neg1=%s, neg2=%s\n",
log_id(module), log_id(neg1), log_id(neg2));
log(" neg1=%s, neg2=%s\n", log_id(neg1), log_id(neg2));
autoremove(neg1);
autoremove(neg2);

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@ -100,8 +100,8 @@ code add_a add_b add_y neg1_a neg1_y neg2_a neg2_y add_signed add_b_signed neg1_
neg_out_rs.extend_u0(GetSize(add_y), add_signed);
module->connect(add_y, neg_out_rs);
log("negrebuild pattern in %s: add=%s, neg1=%s, neg2=%s\n",
log_id(module), log_id(add), log_id(neg1), log_id(neg2));
log(" add=%s, neg1=%s, neg2=%s\n",
log_id(add), log_id(neg1), log_id(neg2));
new_add->fixup_parameters();
new_neg->fixup_parameters();

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@ -43,8 +43,8 @@ code sub_a sub_b sub_y a_signed b_signed
sub->setPort(\Y, sub_y);
sub->type = $add;
log("sub2neg pattern in %s: sub=%s -> neg=%s, add=%s\n",
log_id(module), log_id(sub), log_id(neg), log_id(sub));
log(" sub=%s -> neg=%s, add=%s\n",
log_id(sub), log_id(neg), log_id(sub));
sub->fixup_parameters();
neg->fixup_parameters();