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18230 Commits

Author SHA1 Message Date
Emil J. Tywoniak 3bfeaee8ca opt_expr: fix const lhs of $pow to $shl 2026-02-03 11:59:00 +01:00
Miodrag Milanović 6dbe03f0f5
Merge pull request #5667 from Logikable/vhdl 
Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.
 2026-02-03 07:59:52 +01:00
github-actions[bot] 153ddc0c84 Bump version 2026-02-03 00:33:37 +00:00
AdvaySingh1 2f3ed06b9b ABC: Added setify to reduce number of entries 2026-02-02 15:30:49 -08:00
Sean Luchen 224549fb88 Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT. 
Signed-off-by: Sean Luchen <seanluchen@google.com>
 2026-02-02 15:26:03 -08:00
AdvaySingh1 1317cbbb62 ABC: Added r flag into Extra_UtilGetopt for IoCommandReadBlif 2026-02-02 14:13:18 -08:00
AdvaySingh1 07e21e763a ABC: Refactored fEnabled flag 2026-02-02 14:03:07 -08:00
AdvaySingh1 f452702017 Added abc.node_retention flag 2026-02-02 12:08:18 -08:00
KrystalDelusion 414b1b6019
Merge pull request #5651 from rocallahan/abc-error-nonfatal 
Handle ABC nonfatal "Error:" messages
 2026-02-03 08:55:05 +13:00
AdvaySingh1 47469c2490 Added re-added gateinit logic previously deleted 2026-02-02 10:32:32 -08:00
Emil J 59653da599
Merge pull request #5609 from nataliakokoromyti/upstream-design-run-pass 
Add Design::run_pass()
 2026-02-02 19:30:18 +01:00
AdvaySingh1 900f8408af Fixed read_until_abc_done 2026-02-02 10:27:33 -08:00
AdvaySingh1 b005f69e27 Added comments in blifparse.cc 2026-02-02 10:15:59 -08:00
AdvaySingh1 9646319098 Fixed source wire to be reset to nullptr so value isn't carried on 2026-02-02 10:10:01 -08:00
AdvaySingh1 15625f56ed Removed cmath arbitrary include 2026-02-02 10:08:41 -08:00
AdvaySingh1 b6c1d2fd27 Merge branch 'main' into nr_cleanup 2026-02-02 09:43:42 -08:00
AdvaySingh1 625d2caeaf ABC: Stylistic abc fixes 2026-02-02 09:41:47 -08:00
Miodrag Milanović f5c8368f7a
Merge pull request #5662 from YosysHQ/update_abc 
Update ABC as per 2026-02-02
 2026-02-02 13:44:56 +01:00
Miodrag Milanovic b88d6588bc Update ABC as per 2026-02-02 2026-02-02 11:25:57 +01:00
Akash Levy 7c70026610 Fix verific issue 2026-02-01 00:16:10 -08:00
Akash Levy bdc9ad9f53 Bump version 2026-01-30 19:29:00 -08:00
Akash Levy 462caedc1c Merge fixups 2026-01-30 18:35:53 -08:00
AdvaySingh1 fc61433faa Reducing verbosity for cell printing 2026-01-30 13:11:36 -08:00
AdvaySingh1 7dab62cb42 ABC cleanup 2026-01-30 12:43:59 -08:00
AdvaySingh1 d7a3b4e312 Removed extraneous readblif knob from abc.cc 2026-01-30 12:42:55 -08:00
AdvaySingh1 3b4574b648 abc.cc node_retention pass cleanup 2026-01-30 12:00:12 -08:00
AdvaySingh1 d7aca59e27 Updated abc.cc and blifparse.cc 2026-01-30 11:22:00 -08:00
Miodrag Milanović ac427a79b0
Merge pull request #5644 from nataliakokoromyti/upstream-linux-perf-unistd 
Add unistd header for Linux
 2026-01-30 08:17:43 +01:00
Miodrag Milanović 382b28acbe
Merge pull request #5648 from YosysHQ/verific_moreopts 
verific: fixed -sv2017 option and added ability to set VHDL standard
 2026-01-30 08:17:19 +01:00
Akash Levy 892ef37b26 Undo 2026-01-29 19:36:36 -08:00
Akash Levy bbdf5042c7 Add PYTHON_INCLUDE_FLAGS 2026-01-29 19:20:46 -08:00
Robert O'Callahan 9c56c93632 Add missing newlines to some 'log_error's 2026-01-30 01:52:19 +00:00
Robert O'Callahan 6af1b5b19c Don't treat ABC 'Error:' output as indicating a fatal error, since these messages aren't necessarily fatal 2026-01-30 01:52:19 +00:00
Akash Levy a9cf998f9f Merge from upstream 2026-01-29 17:46:44 -08:00
github-actions[bot] 106f289e31 Bump version 2026-01-30 00:30:58 +00:00
KrystalDelusion 5a4ad6a6d0
Merge pull request #5640 from YosysHQ/krys/fix_mod.py 
Don't use `module mod_name(...)` style in cell libs
 2026-01-30 11:40:07 +13:00
Emil J a68fee1115
Merge pull request #5646 from rocallahan/debug-design_equal 
Dump module details when `design_equal` fails
 2026-01-29 18:57:24 +01:00
Natalia 61b1c3c75a use run_pass in ecp5 add/sub test 2026-01-29 02:42:23 -08:00
Natalia 7439d2489e add assertion to run_pass test 2026-01-29 02:23:07 -08:00
Miodrag Milanovic b70f527c67 verific: fixed -sv2017 option and added ability to set VHDL standard if applicable 2026-01-29 10:32:30 +01:00
Miodrag Milanović 6ba8f3dc19
Merge pull request #5647 from YosysHQ/update_abc 
ABC update (MINGW fix)
 2026-01-29 10:12:25 +01:00
Miodrag Milanović 43db5c9488
Merge pull request #5645 from nataliakokoromyti/upstream-verific-mixed-sv-vhdl 
Upstream verific mixed sv vhdl
 2026-01-29 10:12:09 +01:00
Miodrag Milanovic 6007b68e9c ABC update (MINGW fix) 2026-01-29 09:30:12 +01:00
Natalia 8d504ecb48 verific: use MFCU for SV file list 2026-01-29 00:03:28 -08:00
Akash Levy 1dd846022b Fix opt_dff cell naming 2026-01-28 23:36:49 -08:00
Natalia b6c148f84a tests/verific: ensure mixed -f requires VHDL unit 2026-01-28 22:46:10 -08:00
Akash Levy 9f911e3d63 Reorder ff.remove in opt_dff 2026-01-28 20:58:01 -08:00
Akash Levy 5993d2fec8 Remove annoying test case 2026-01-28 19:18:06 -08:00
Akash Levy bb2aadb9ef Merge remote-tracking branch 'upstream/main' 2026-01-28 19:09:56 -08:00
Akash Levy 4e937450b4
Merge pull request #97 from Silimate/reg-rename 
Bug fix for reg_rename pass
 2026-01-28 19:08:26 -08:00