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2298 Commits

Author SHA1 Message Date
George Rennie ab40403d90
Merge pull request #5154 from georgerennie/george/post_incdec_undo_fix 
read_verilog: fix -1 constant used to correct post increment/decrement
 2025-06-04 14:22:32 +01:00
Emil J. Tywoniak c37b7b3bf4 simplify: fix single_bit_vector memory leak 2025-06-04 10:32:03 +02:00
Akash Levy e3a6b920d4
Merge branch 'YosysHQ:main' into main 2025-06-02 18:47:14 +02:00
Gary Wong ca7d94af99 verilog: improve string literal matching speed (fixes #5076) 
Use a greedy regular expression to match input inside a string
literal, so that flex can accumulate a longer match instead of
invoking a rule for each individual character.
 2025-05-31 22:38:44 -06:00
George Rennie 45e8ff476e read_verilog: copy inout ports in and out of functions/tasks 2025-05-31 01:09:03 +01:00
KrystalDelusion 545753cc5a
Merge pull request #5143 from YosysHQ/krys/typedef_struct_global 
SystemVerilog: Fix typedef struct in global space
 2025-05-31 09:59:26 +12:00
George Rennie 70291f0e49 read_verilog: fix -1 constant used to correct post increment/decrement 2025-05-30 14:38:25 +01:00
Gary Wong 370d5871f4 verilog: implement SystemVerilog unique/unique0/priority if semantics. 
There are two elements involved:

1) Apply the relevant full_case and/or parallel_case attribute(s) to
the generated AST_CASE node(s), so that the existing AST frontend and
subsequent passes will generate RTLIL with appropriate behaviour.
(This is handled in the parser "if_attr" non-terminal.)

2) Rearrange the AST_CASE structure when necessary.  For "priority if"
(i.e., full_case), this requires only ensuring that directly nested
"else if" branches also inherit the full_case attribute.  For
"unique if" and "unique0 if" (i.e., parallel_case+full_case and
parallel_case alone), there are two steps:
    a) Flatten the AST_CASE structure such that any direct "else if"
    branches are mapped to additional AST_CONDs in the parent;
    b) Reverse the "direction" of the test: the constant 1 (true)
    is provided in the AST_CASE node, and the expression(s) in the
    if statement(s) are given in each AST_COND.  This is necessary
    because the constant 1, being the common factor, must occupy the
    shared AST_CASE position.
(This is handled in the parser "TOK_IF" expansion of behavioral_stmt.)

Observe that:
 * The generated AST has not been changed for bare "if"s (those
 without unique/priority).  This should minimise the risk of
 unexpected regressions.

 * It is possible that the flattening described in 2) a) above might
 affect the behaviour of expressions with side effects in "unique if"
 statements (consider "unique if( a ) ...; else if( b++ ) ...": if
 a is true, is b incremented?).  While it might be possible to provide
 precise semantics here, IEEE 1800-2012 12.4.2 seems to be deliberately
 vague ("In unique-if and unique0-if, the conditions may be evaluated
 and compared in any order[...] The presence of side effects in
 conditions may cause nondeterministic results.") and so it seems
 doubtful that there is benefit in Yosys providing stronger promises
 on the interpretation of questionable code.
 2025-05-29 20:45:57 -06:00
Akash Levy e50a5974f7 Get rid of SYNTHESIS redefinition warning 2025-05-28 08:33:56 +02:00
Akash Levy 3fc74be3e2
Merge branch 'YosysHQ:main' into main 2025-05-28 01:54:49 +02:00
KrystalDelusion 489a12d6c1
Merge pull request #5141 from garytwong/unique-if 
Accept (and ignore) SystemVerilog unique/priority if.
 2025-05-27 09:45:50 +12:00
Krystine Sherwin 32ce23458f
read_verilog: Mark struct as custom type 
Being a custom type means that it will be resolved *before* (e.g.) a wire can use it as a type.
 2025-05-26 12:19:33 +12:00
Akash Levy 3a23e772dd
Merge branch 'YosysHQ:main' into main 2025-05-24 12:11:52 -07:00
Emil J 4b8d42d22c
Merge pull request #5095 from YosysHQ/emil/one-bit-width 
rtlil: enable single-bit vector wires
 2025-05-23 15:55:45 +02:00
Gary Wong 9770ece187 Accept (and ignore) SystemVerilog unique/priority if. 
Add support to the "read_verilog -sv" parser to validate the
"unique", "unique0", and "priority" keywords in contexts where
they're legal according to 1800-2012 12.4.2.

This affects only the grammar accepted; the behaviour of conditionals
is not changed.  (But accepting this syntax will provide scope for
possible optimisations as future work.)

Three test cases ("unique_if", "unique_if_else", and
"unique_if_else_begin") verify that the keywords are accepted where
legal and rejected where illegal, as described in the final paragraph
of 12.4.2.
 2025-05-22 19:28:28 -06:00
Akash Levy ccc2ba41f2
Merge branch 'YosysHQ:main' into main 2025-05-12 15:02:55 -07:00
Emil J. Tywoniak e5171d6aa1 verific: support single_bit_vector 2025-05-12 13:23:29 +02:00
Emil J. Tywoniak 5e72464a15 rtlil: enable single-bit vector wires 2025-05-12 13:23:29 +02:00
Krystine Sherwin fe0abb7026
simplify.cc: Fix mem leak 2025-05-10 17:10:47 +12:00
Akash Levy 3bcbfe4dde verific -set_relaxed_file_libext_modes 2025-05-08 23:43:23 -07:00
Akash Levy f3d24aea76 Add spaces in verific 2025-05-08 22:24:10 -07:00
Akash Levy 380850321d Refactor verific -optimization and -no_split_complex_ports into verific pass 2025-05-08 15:59:47 -07:00
KrystalDelusion 547382504b
Update verilog_frontend.cc 
`read_verilog_file_list` should not try to read arguments as selection args.  Without this, trying to pass a file without a `-f|-F` flag is misleading, in the best case giving a warning about the selection not matching any module, or in worst case just doing nothing (if the filename is a valid selection).
 2025-05-08 10:37:04 +12:00
Akash Levy 7191be492c
Merge branch 'YosysHQ:main' into main 2025-05-05 15:36:40 -07:00
Krystine Sherwin 23cb007068
verilog_parser.y: Delete unused TOK_ID 
Fixes memory leak when parameter has no value.
 2025-05-05 10:04:13 +12:00
Akash Levy 618cf9d372
Merge branch 'YosysHQ:main' into main 2025-04-28 13:57:29 -07:00
N. Engelhardt 8bdbf797d0
Merge pull request #5017 from YosysHQ/micko/ram_blasting 2025-04-28 13:33:48 +00:00
Akash Levy 94bc6937d3
Merge branch 'YosysHQ:main' into main 2025-04-27 15:24:30 -07:00
Emil J. Tywoniak bdc2597f79 simplify: fix struct wiretype attr memory leak 2025-04-25 01:00:08 +02:00
Miodrag Milanovic 22e6ce4282 verific: bit blast RAM if using mem2reg attribute 2025-04-14 15:24:11 +02:00
Akash Levy 3e24a3e248 Bump yosys to latest 2025-04-08 18:05:28 -07:00
Miodrag Milanovic 406ee4c8d3 read_verilog_file_list: change short help message to start with lower case 2025-04-08 13:20:16 +02:00
Akash Levy 06c614a010
Merge branch 'YosysHQ:main' into main 2025-04-07 07:28:06 -07:00
Akash Levy 61715c2c28 Fix memory too large issue 2025-04-04 03:22:22 -07:00
Akash Levy f218b5ba58 Revert "Represent memory size with size_t" 
This reverts commit bb5f8415af.
 2025-04-04 03:20:07 -07:00
Akash Levy bb5f8415af Represent memory size with size_t 2025-04-04 02:04:34 -07:00
Jannis Harder 0f13b55173 Liberty file caching with new `libcache` command 
This adds optional in-memory caching of parsed liberty files to speed up
flows that repeatedly parse the same liberty files. To avoid increasing
the memory overhead by default, the caching is disabled by default. The
caching can be controlled globally or on a per path basis using the new
`libcache` command, which also allows purging cached data.
 2025-04-03 13:39:35 +02:00
Akash Levy 4bd08ac362
Merge branch 'YosysHQ:main' into main 2025-04-01 22:10:43 -07:00
Miodrag Milanovic 72f2185a94 verific: fix restoring msg state after blackbox import 2025-04-01 17:35:59 +02:00
Akash Levy d2028feefe Set Verific flags via -cfg instead of in Yosys 2025-03-25 22:41:06 -07:00
Krystine Sherwin 0a1c664f02
simplify: Skip AST_PRIMITIVE in AST_CELLARRAY 
Otherwise the `AST_PRIMITIVE` simplifies to the corresponding function and is no longer caught by the check for `AST_PRIMITIVE`s, raising an assertion error instead of an input error.
Add bug4785.ys to tests/verilog to demonstrate.
 2025-03-25 12:15:54 +13:00
Akash Levy 95f489beec Merge nice gzip refactor 2025-03-20 16:47:12 -07:00
Emil J. Tywoniak 813f909460 gzip: istream 2025-03-19 13:43:44 +01:00
Emil J. Tywoniak 4f3fdc8457 io: refactor string and file work into new unit 2025-03-19 13:43:42 +01:00
Alain Dargelas 3021dab37d memory limit fix and increased limit 2025-03-17 09:07:33 -07:00
Akash Levy bc3ca6210c Add back operator optimization for Verific frontend 2025-03-17 04:06:28 -07:00
Akash Levy 1c0d4a43b3
Merge branch 'YosysHQ:main' into main 2025-03-14 18:07:55 -07:00
Alain Dargelas 88211310fa code review 2025-03-12 16:32:42 -07:00
Alain Dargelas dcce15207e Memory size check 2025-03-12 16:21:18 -07:00
Jason Xu a5f34d04f8 Address comments 2025-03-11 18:50:44 -04:00
Jason Xu 98eefc5d1a Add file list support to read pass 2025-03-07 20:44:21 -05:00
Jason Xu bf1eab565b Fix compile on WASI platform 2025-03-07 20:20:27 -05:00
Jason Xu ac31bad656 Address all comments 2025-03-07 20:16:28 -05:00
Jason Xu 8ec96ec806 Address most comments 2025-03-07 20:16:28 -05:00
Jason Xu 0678c4dec9 Coding style update 2025-03-07 20:16:28 -05:00
Jason Xu f62a9be153 Initial file list support 2025-03-07 20:16:28 -05:00
Akash Levy 881080a827 Merge upstream 2025-03-05 07:54:26 -08:00
Emil J 39aacc95df
Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch 
liberty: fix clear and preset latches
 2025-03-03 18:53:12 +01:00
Akash Levy 9d3b7f7474
Merge branch 'YosysHQ:main' into main 2025-02-26 09:51:44 -08:00
Martin Povišer 732ed67014 ast/dpicall: Stop using variable length array 
Fix the compiler warning

    variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]
 2025-02-24 17:32:30 +01:00
Emil J. Tywoniak 2b33937ab8 liberty: fix clear and preset latches 2025-02-17 17:36:51 +01:00
Akash Levy fd811ddaee Cleanup 2025-02-14 08:48:27 -08:00
Akash Levy f76fd9280b Clean up Verific 2025-02-14 06:56:20 -08:00
Akash Levy c8c97ea00b Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
Akash Levy 47aac95f64 Fix incdir, ydir, libext issues 2025-02-05 05:58:49 -08:00
Akash Levy 993b23e747 Merge upstream 2025-02-03 09:33:16 -08:00
KrystalDelusion cf52cf3009
nowrshmsk: Check for stride==0 
log2(0) returns -inf, which gives undefined behaviour when casting to an int.  So catch the case when it's 0 just set the width to 0.
 2025-01-31 12:15:53 +13:00
Akash Levy bd439fc524 Reapply "Merge upstream" 
This reverts commit e73d51dbf0.
 2025-01-23 13:40:32 -08:00
Akash Levy e73d51dbf0 Revert "Merge upstream" 
This reverts commit c58a50f880, reversing
changes made to a1c3c98773.
 2025-01-21 05:28:36 -08:00
Akash Levy c58a50f880 Merge upstream 2025-01-21 04:36:34 -08:00
Akash Levy a1c3c98773 Messed up usage of SILIMATE_VERIFIC_EXTENSIONS 2025-01-21 00:12:28 -08:00
Akash Levy da726a4e54 If imported module has parameters it is not a blackbox 2025-01-17 01:14:40 -08:00
N. Engelhardt d640157ec4 fix some cases of hdlname being added to objects with private names 2025-01-15 15:56:42 +01:00
Akash Levy 57bf3a6f51
Merge branch 'YosysHQ:main' into main 2025-01-14 08:38:59 -08:00
Emil J. Tywoniak a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak 4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Akash Levy 1eee11846e Resolve reg naming to some extent 2024-12-17 12:11:39 -08:00
Akash Levy 1242db626f Merge remote-tracking branch 'upstream/main' 2024-12-12 22:49:19 -08:00
N. Engelhardt 378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
Akash Levy caaef5ac14
Merge branch 'YosysHQ:main' into main 2024-12-11 12:00:34 -08:00
N. Engelhardt 03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Martin Povišer ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes 
Support `abc9_box` on ordinary modules in abc_new
 2024-12-10 20:07:56 +01:00
Martin Povišer e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells 
read_liberty: Revisit for abc9 whiteboxes
 2024-12-10 17:50:21 +01:00
Martin Povišer 6b343c2600 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
Akash Levy e0ba08dd1d
Merge branch 'YosysHQ:main' into main 2024-12-09 11:13:47 -08:00
Martin Povišer a353b8fff0 read_liberty: Directly set `abc9_box` on fitting cells 2024-12-09 15:43:41 +01:00
Miodrag Milanovic 7d4aff618f verific: Disable module existence check during static elaboration 2024-12-06 15:59:09 +01:00
Akash Levy c720175c73
Merge branch 'YosysHQ:main' into main 2024-12-05 13:54:47 -08:00
Martin Povišer cf0a583f40 read_xaiger2: Rm debug print 2024-12-05 18:33:20 +01:00
Martin Povišer 5dffdd229c read_liberty: Redo unit delay; add `simple_comb_cell` attr 2024-12-05 18:31:24 +01:00
Akash Levy 4356eae4c9 Yosys sync 2024-12-04 14:16:55 -08:00
KrystalDelusion c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings 
Reduce number of warnings
 2024-12-05 09:16:06 +13:00
Akash Levy 7847b1b2eb
Merge pull request #30 from alaindargelas/macro_power 
Simulation information for macro power
 2024-12-04 10:01:04 -08:00
Alain Dargelas 350b04daa3 Ignore unused modules 2024-12-03 13:00:14 -08:00
Krystine Sherwin e634e9c26b
aiger2: Resolve warnings 
- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
 2024-12-03 14:01:57 +13:00
Akash Levy e0cef06b52
Merge branch 'YosysHQ:main' into main 2024-12-02 19:39:14 -05:00
Miodrag Milanovic 912b38eedb verific: Handle crash when using empty box option 2024-12-02 15:45:12 +01:00
Akash Levy ead4b34c3c Add stack include to decorate_loops.h 2024-12-01 16:50:51 -05:00
Akash Levy 620bf51c50
Merge pull request #29 from alaindargelas/loop_info_3 
Selective boolopt
 2024-12-01 12:36:09 -05:00
Akash Levy 6e88c689f2
Merge branch 'YosysHQ:main' into main 2024-12-01 12:32:07 -05:00
Krystine Sherwin 1de5d98ae2
Reduce comparisons of size_t and int 
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
 2024-11-29 12:53:29 +13:00
Martin Povišer 3bab837bc9
Merge pull request #4765 from georgerennie/george/rtlil_case_rule 
read_rtlil: Warn on assigns after switches in case rules
 2024-11-28 00:01:21 +01:00
Alain Dargelas c32d0a412c Selective boolopt 2024-11-25 15:08:42 -08:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Akash Levy c3d6821f7d Removing compiler warnings and errors 2024-11-22 20:04:39 -08:00
George Rennie 4a057b3c44 read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
Alain Dargelas 97f5ef2056 indent 2024-11-21 11:31:36 -08:00
Alain Dargelas dc9d61ed61 Loop info 2024-11-21 11:24:00 -08:00
Alain Dargelas 179bd25235 Loop info 2024-11-21 11:23:13 -08:00
Alain Dargelas dde6a8d8f1 Loop info 2024-11-21 11:20:40 -08:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Akash Levy bbbc292209 Smallfixes 2024-11-20 21:10:58 -08:00
Akash Levy 6a7e2d2572 Beginnings of UPF support 2024-11-20 20:36:29 -08:00
Akash Levy 2b39770f57 Update flags to be better 2024-11-20 20:36:12 -08:00
Akash Levy 06c87f6a2d Smallfix 2024-11-19 17:42:36 -08:00
Akash Levy 5eaf627645 Undo Liberty stuff 2024-11-18 17:10:25 -08:00
Akash Levy 1a69c51c88
Merge branch 'YosysHQ:main' into main 2024-11-18 16:10:30 -08:00
Martin Povišer 1cb5fd08b7
Merge pull request #4682 from povik/read_liberty-extensions 
read_liberty extensions
 2024-11-18 14:42:18 +01:00
Akash Levy df0ce40841 blif fixes 2024-11-16 21:53:06 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
Mike Inouye 06e3ac4415 Fix bug when setting Verific runtime string flags. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-11-12 18:46:26 +00:00
Martin Povišer 0d5c412807 read_liberty: s/busses/buses/ 2024-11-12 13:33:41 +01:00
Martin Povišer 28aa7b00ee read_liberty: Start an `-ignore_busses` option 2024-11-12 13:26:38 +01:00
Martin Povišer 0e96e477a2 read_liberty: Defer handling of re-definitions 
Postpone handling re-definitions to after we have established the cell
is not supposed to be ignored on the grounds of one of the user-provided
flags.
 2024-11-12 13:26:38 +01:00
Martin Povišer c7e8d41600 read_liberty: Set `area` `capacitance` attributes 2024-11-12 13:26:38 +01:00
Akash Levy a3b4789934 Smallfixes 2024-11-12 02:32:03 -08:00
Akash Levy 86d321a306 Undo blif frontend stuff 2024-11-12 01:30:06 -08:00
Akash Levy 83234d24f7 Switch from Synopsys register naming to preserve 2024-11-11 17:06:56 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Akash Levy fa50434708
Merge branch 'YosysHQ:main' into main 2024-11-08 14:10:24 -08:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Akash Levy 1cba744712 Update 2024-11-04 17:01:41 -08:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
George Rennie dbfca1bdff frontends/ast.cc: special-case zero width strings as "\0" 
* Fixes #4696
 2024-11-01 17:19:28 +01:00
Alain Dargelas 615f523ef4 pass no_split_complex_ports to hierarchy command 2024-10-29 13:37:03 -07:00
Akash Levy 5e606722e3 Get autoidx reset working 2024-10-28 16:30:47 -07:00
Akash Levy 038c562493 VHDL support fix 2024-10-25 11:32:52 -07:00
Akash Levy 8e667e2e9f Add documentation for VHDL library directory 2024-10-23 23:53:21 -07:00
Akash Levy 17c8567b02 Really tiny fixes 2024-10-23 22:03:00 -07:00
Akash Levy 3d127dff4a Add set VHDL default library path 2024-10-21 01:22:56 -07:00
Akash Levy c94eac14b9 Remove GHDL and add mixed SV-VHDL support 2024-10-20 23:29:33 -07:00
Akash Levy e2659247fc Verific UPF eval working 2024-10-17 04:40:38 -07:00
Akash Levy cafd4cbbe8
Merge branch 'YosysHQ:main' into main 2024-10-15 06:43:06 -07:00
Emil J. Tywoniak 81bbde62ca verilog_parser: silence yynerrs warning 2024-10-15 08:32:55 -04:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip 
Represent string constants as strings
 2024-10-14 06:42:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanovic 8d2b63bb8a Set VHDL assert condition initial state if fed by FF 2024-10-11 16:32:21 +02:00
Akash Levy 48cb802599 Undo bound removal 2024-10-10 13:34:18 -07:00
Akash Levy fdc4c54c66
Merge branch 'YosysHQ:main' into main 2024-10-07 07:27:27 -10:00
Martin Povišer 0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay 
read_liberty: Optionally import unit delay arcs
 2024-10-07 16:11:51 +02:00
Martin Povišer 74e92d10e8
Merge pull request #4593 from povik/aiger2 
New aiger backend
 2024-10-07 16:11:25 +02:00
Martin Povišer 7989d53c58 read_xaiger2: Add help 2024-10-07 14:19:49 +02:00
Martin Povišer f44a418212 read_xaiger2: Add casts to silence warnings 2024-10-07 12:27:54 +02:00
Martin Povišer 8d12492610 read_xaiger2: Fix detecting the end of extensions 2024-10-07 12:03:48 +02:00
Martin Povišer 2b1b5652f1 Adjust `read_xaiger2` prints 2024-10-07 12:03:48 +02:00
Akash Levy f76cb43ac7 Add bundle support 2024-10-05 01:35:03 -10:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy 5038bfa2af Fix minor whitespace thing 2024-10-03 00:29:16 -07:00
Akash Levy ec296736f5 Simplify multiport 2024-10-02 22:19:09 -07:00
Akash Levy 400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy 8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Akash Levy ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy ee0b083a1e
Merge branch 'YosysHQ:main' into main 2024-09-30 02:43:09 -07:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Akash Levy 0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy 5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy 0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy 0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy 69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy 89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy 7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy 4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy 7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy 2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Martin Povišer f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer 1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer 4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
Akash Levy 44789c9f6c Move ram opt around 2024-09-16 18:56:48 -07:00
Akash Levy 285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Akash Levy 985de62d3c
Merge branch 'YosysHQ:main' into main 2024-09-11 16:01:37 -07:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Akash Levy ce95ec1f9e Add VHDL support via GHDL call 2024-09-05 13:24:38 -07:00
Akash Levy 57446f3f93
Merge branch 'YosysHQ:main' into master 2024-08-21 18:52:38 -07:00
Akash Levy 6e46a56720 Fix Verific warning 2024-08-21 16:55:44 -07:00
Roland Coeurjoly 27c1432253 Remove log 2024-08-21 14:28:42 +01:00
Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Akash Levy dba9a26cf3 Make default macros optional 2024-08-21 00:50:10 -07:00
Akash Levy 34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Martin Povišer ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer 309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Akash Levy 68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Miodrag Milanović 3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Miodrag Milanovic 405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
Akash Levy f790b75c19 Don't preserve user nets and update Verific tree balancing 2024-07-25 06:01:06 -07:00
Miodrag Milanovic 9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Akash Levy f1114cc98c Simplify ignores 2024-07-24 02:14:11 -07:00
Akash Levy ebc9f96f85
Merge branch 'YosysHQ:main' into master 2024-07-23 15:01:54 -07:00
Miodrag Milanovic c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00
Emil J. Tywoniak 72a0380da8 ast: don't suggest use in external projects 2024-07-18 16:37:14 +02:00
Akash Levy f18ddb5db2 Remove wide operator control 2024-07-10 12:53:59 -07:00
Akash Levy 8f4b66ae77 Set db_infer_wide_operators externally 2024-07-08 08:32:34 -07:00
Akash Levy 70016a08b8 Disable debug 2024-07-03 06:55:53 -07:00
Akash Levy 30241e07eb Fix segfault 2024-07-03 02:29:48 -07:00
Akash Levy fcd073ab51 Smallfix 2024-07-02 15:13:58 -07:00
Akash Levy 0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Akash Levy dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
gatecat 22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy 719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Akash Levy a0c0384683 Preserve instances 2024-06-16 20:20:10 -07:00
Akash Levy e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00
Akash Levy 2337d97977 Sub1 fix 2024-06-13 15:33:17 -07:00
Akash Levy ac0a9e7366 Updates 2024-06-10 20:52:11 -07:00
Akash Levy b9b776d211 Update for no preservation of user nets 2024-06-10 20:33:05 -07:00
Martin Povišer b593f5c01c Update the overview comment in `ast.h` 2024-06-10 16:38:39 +02:00
Akash Levy d930310599 Enable more updates 2024-06-09 13:54:34 -07:00
Mike Inouye b0ab1cf8c3 Fix memory leak in verific file parsing. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-06-07 22:51:28 +00:00
Akash Levy 8499d31cf2 Revert veri_break_loops setting 2024-06-07 00:09:01 -07:00
Akash Levy c8f7441a4a Fix skip default value 2024-06-05 09:33:03 -07:00
Akash Levy c59a997255 Ignore files properly 2024-06-05 07:53:21 -07:00
Akash Levy 4d44099d09 Support for ignoring translate_off and ignoring files 2024-06-05 05:00:05 -07:00
Akash Levy 5dc62bec0b Support .inc files and readmemh missing file 2024-06-03 20:05:30 -07:00
Akash Levy 92e44cc9a3 Minor fix to ignore files 2024-06-03 18:17:50 -07:00
Akash Levy 4339b3681a Elaborate top level modules undo 2024-06-03 16:17:51 -07:00
Akash Levy a692bf17d7 Improper ignore translates 2024-06-03 11:23:16 -07:00
Akash Levy 783c0a593a Actually optimize with Verific now 2024-06-03 04:55:47 -07:00
Akash Levy 4475b50ffa Undo some ugly stuff and make more attempted fixes 2024-06-02 23:33:23 -07:00
Akash Levy 2585636d18 Use ability to get/set IMPORT runtime flags 2024-06-02 22:24:29 -07:00