mirror of https://github.com/YosysHQ/yosys.git
Undo
This commit is contained in:
parent
ff0fd570d8
commit
8bf86e8d1f
|
|
@ -1649,7 +1649,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma
|
|||
cell->parameters[ID::MEMID] = RTLIL::Const(memory->name.str());
|
||||
cell->parameters[ID::ABITS] = 32;
|
||||
cell->parameters[ID::WIDTH] = memory->width;
|
||||
cell->parameters[ID::PRIORITY] = 0;
|
||||
cell->parameters[ID::PRIORITY] = RTLIL::Const(autoidx-1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue