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2298 Commits

Author SHA1 Message Date
Jason Xu 98eefc5d1a Add file list support to read pass 2025-03-07 20:44:21 -05:00
Jason Xu bf1eab565b Fix compile on WASI platform 2025-03-07 20:20:27 -05:00
Jason Xu ac31bad656 Address all comments 2025-03-07 20:16:28 -05:00
Jason Xu 8ec96ec806 Address most comments 2025-03-07 20:16:28 -05:00
Jason Xu 0678c4dec9 Coding style update 2025-03-07 20:16:28 -05:00
Jason Xu f62a9be153 Initial file list support 2025-03-07 20:16:28 -05:00
Akash Levy 881080a827 Merge upstream 2025-03-05 07:54:26 -08:00
Emil J 39aacc95df
Merge pull request #4907 from YosysHQ/emil/fix-clear-preset-latch 
liberty: fix clear and preset latches
 2025-03-03 18:53:12 +01:00
Akash Levy 9d3b7f7474
Merge branch 'YosysHQ:main' into main 2025-02-26 09:51:44 -08:00
Martin Povišer 732ed67014 ast/dpicall: Stop using variable length array 
Fix the compiler warning

    variable length arrays in C++ are a Clang extension [-Wvla-cxx-extension]
 2025-02-24 17:32:30 +01:00
Emil J. Tywoniak 2b33937ab8 liberty: fix clear and preset latches 2025-02-17 17:36:51 +01:00
Akash Levy fd811ddaee Cleanup 2025-02-14 08:48:27 -08:00
Akash Levy f76fd9280b Clean up Verific 2025-02-14 06:56:20 -08:00
Akash Levy c8c97ea00b Revert back to using Verific naming 2025-02-13 19:40:33 -08:00
Akash Levy 47aac95f64 Fix incdir, ydir, libext issues 2025-02-05 05:58:49 -08:00
Akash Levy 993b23e747 Merge upstream 2025-02-03 09:33:16 -08:00
KrystalDelusion cf52cf3009
nowrshmsk: Check for stride==0 
log2(0) returns -inf, which gives undefined behaviour when casting to an int.  So catch the case when it's 0 just set the width to 0.
 2025-01-31 12:15:53 +13:00
Akash Levy bd439fc524 Reapply "Merge upstream" 
This reverts commit e73d51dbf0.
 2025-01-23 13:40:32 -08:00
Akash Levy e73d51dbf0 Revert "Merge upstream" 
This reverts commit c58a50f880, reversing
changes made to a1c3c98773.
 2025-01-21 05:28:36 -08:00
Akash Levy c58a50f880 Merge upstream 2025-01-21 04:36:34 -08:00
Akash Levy a1c3c98773 Messed up usage of SILIMATE_VERIFIC_EXTENSIONS 2025-01-21 00:12:28 -08:00
Akash Levy da726a4e54 If imported module has parameters it is not a blackbox 2025-01-17 01:14:40 -08:00
N. Engelhardt d640157ec4 fix some cases of hdlname being added to objects with private names 2025-01-15 15:56:42 +01:00
Akash Levy 57bf3a6f51
Merge branch 'YosysHQ:main' into main 2025-01-14 08:38:59 -08:00
Emil J. Tywoniak a58481e9b7 mark all hash_into methods nodiscard 2025-01-14 12:39:15 +01:00
Akash Levy 1dcf75d175 Sync 2024-12-19 21:40:30 -08:00
Emil J. Tywoniak b9b9515bb0 hashlib: hash_eat -> hash_into 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak 4e29ec1854 hashlib: acc -> eat 2024-12-18 15:09:25 +01:00
Emil J. Tywoniak d071489ab1 hashlib: redo interface for flexibility 2024-12-18 14:49:25 +01:00
Akash Levy 1eee11846e Resolve reg naming to some extent 2024-12-17 12:11:39 -08:00
Akash Levy 1242db626f Merge remote-tracking branch 'upstream/main' 2024-12-12 22:49:19 -08:00
N. Engelhardt 378864d33b bound attributes: handle vhdl null ranges 2024-12-12 11:42:39 +01:00
Akash Levy caaef5ac14
Merge branch 'YosysHQ:main' into main 2024-12-11 12:00:34 -08:00
N. Engelhardt 03033ab6d4 add more tests for bounds attributes, fix attributes appearing in verilog 2024-12-11 16:11:02 +01:00
Martin Povišer ea38fcca5e
Merge pull request #4737 from povik/abc_new-design-boxes 
Support `abc9_box` on ordinary modules in abc_new
 2024-12-10 20:07:56 +01:00
Martin Povišer e9c7967d1e
Merge pull request #4804 from povik/read_liberty-comb-cells 
read_liberty: Revisit for abc9 whiteboxes
 2024-12-10 17:50:21 +01:00
Martin Povišer 6b343c2600 aiger2: Clean debug print 2024-12-10 14:27:55 +01:00
Akash Levy e0ba08dd1d
Merge branch 'YosysHQ:main' into main 2024-12-09 11:13:47 -08:00
Martin Povišer a353b8fff0 read_liberty: Directly set `abc9_box` on fitting cells 2024-12-09 15:43:41 +01:00
Miodrag Milanovic 7d4aff618f verific: Disable module existence check during static elaboration 2024-12-06 15:59:09 +01:00
Akash Levy c720175c73
Merge branch 'YosysHQ:main' into main 2024-12-05 13:54:47 -08:00
Martin Povišer cf0a583f40 read_xaiger2: Rm debug print 2024-12-05 18:33:20 +01:00
Martin Povišer 5dffdd229c read_liberty: Redo unit delay; add `simple_comb_cell` attr 2024-12-05 18:31:24 +01:00
Akash Levy 4356eae4c9 Yosys sync 2024-12-04 14:16:55 -08:00
KrystalDelusion c96d02b204
Merge pull request #4784 from YosysHQ/krys/reduce_warnings 
Reduce number of warnings
 2024-12-05 09:16:06 +13:00
Akash Levy 7847b1b2eb
Merge pull request #30 from alaindargelas/macro_power 
Simulation information for macro power
 2024-12-04 10:01:04 -08:00
Alain Dargelas 350b04daa3 Ignore unused modules 2024-12-03 13:00:14 -08:00
Krystine Sherwin e634e9c26b
aiger2: Resolve warnings 
- Remove unused statics CONST_FALSE and CONST_TRUE (which appear to have been folded into the `Index` declaration as CFALSE and CTRUE).
- Assign default value of EMPTY_LIT to `a` and `b` for comparison ops.
- Tag debug only variables with YS_MAYBE_UNUSED, don't assign unused variables (but continue to call the function because it moves the file pointer).
 2024-12-03 14:01:57 +13:00
Akash Levy e0cef06b52
Merge branch 'YosysHQ:main' into main 2024-12-02 19:39:14 -05:00
Miodrag Milanovic 912b38eedb verific: Handle crash when using empty box option 2024-12-02 15:45:12 +01:00
Akash Levy ead4b34c3c Add stack include to decorate_loops.h 2024-12-01 16:50:51 -05:00
Akash Levy 620bf51c50
Merge pull request #29 from alaindargelas/loop_info_3 
Selective boolopt
 2024-12-01 12:36:09 -05:00
Akash Levy 6e88c689f2
Merge branch 'YosysHQ:main' into main 2024-12-01 12:32:07 -05:00
Krystine Sherwin 1de5d98ae2
Reduce comparisons of size_t and int 
`Const::size()` returns int, so change iterators that use it to `auto` instead of `size_t`.
For cases where size is being explicitly cast to `int`, use the wrapper that we already have instead: `Yosys::GetSize()`.
 2024-11-29 12:53:29 +13:00
Martin Povišer 3bab837bc9
Merge pull request #4765 from georgerennie/george/rtlil_case_rule 
read_rtlil: Warn on assigns after switches in case rules
 2024-11-28 00:01:21 +01:00
Alain Dargelas c32d0a412c Selective boolopt 2024-11-25 15:08:42 -08:00
Miodrag Milanović 29e8812bab
Merge pull request #4724 from YosysHQ/micko/blackbox_verific 
verific: fix blackbox regression and add test case
 2024-11-25 15:06:54 +01:00
Akash Levy c3d6821f7d Removing compiler warnings and errors 2024-11-22 20:04:39 -08:00
George Rennie 4a057b3c44 read_rtlil: warn on assigns after switches in case rules 2024-11-21 22:41:13 +01:00
Alain Dargelas 97f5ef2056 indent 2024-11-21 11:31:36 -08:00
Alain Dargelas dc9d61ed61 Loop info 2024-11-21 11:24:00 -08:00
Alain Dargelas 179bd25235 Loop info 2024-11-21 11:23:13 -08:00
Alain Dargelas dde6a8d8f1 Loop info 2024-11-21 11:20:40 -08:00
Miodrag Milanovic d6bd521487 verific : VHDL assert DFF initial value set on Verific library patch side 2024-11-21 13:43:26 +01:00
Akash Levy bbbc292209 Smallfixes 2024-11-20 21:10:58 -08:00
Akash Levy 6a7e2d2572 Beginnings of UPF support 2024-11-20 20:36:29 -08:00
Akash Levy 2b39770f57 Update flags to be better 2024-11-20 20:36:12 -08:00
Akash Levy 06c87f6a2d Smallfix 2024-11-19 17:42:36 -08:00
Akash Levy 5eaf627645 Undo Liberty stuff 2024-11-18 17:10:25 -08:00
Akash Levy 1a69c51c88
Merge branch 'YosysHQ:main' into main 2024-11-18 16:10:30 -08:00
Martin Povišer 1cb5fd08b7
Merge pull request #4682 from povik/read_liberty-extensions 
read_liberty extensions
 2024-11-18 14:42:18 +01:00
Akash Levy df0ce40841 blif fixes 2024-11-16 21:53:06 -08:00
Akash Levy 6be73e5c2e Updates 2024-11-15 19:02:06 -08:00
Mike Inouye 06e3ac4415 Fix bug when setting Verific runtime string flags. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-11-12 18:46:26 +00:00
Martin Povišer 0d5c412807 read_liberty: s/busses/buses/ 2024-11-12 13:33:41 +01:00
Martin Povišer 28aa7b00ee read_liberty: Start an `-ignore_busses` option 2024-11-12 13:26:38 +01:00
Martin Povišer 0e96e477a2 read_liberty: Defer handling of re-definitions 
Postpone handling re-definitions to after we have established the cell
is not supposed to be ignored on the grounds of one of the user-provided
flags.
 2024-11-12 13:26:38 +01:00
Martin Povišer c7e8d41600 read_liberty: Set `area` `capacitance` attributes 2024-11-12 13:26:38 +01:00
Akash Levy a3b4789934 Smallfixes 2024-11-12 02:32:03 -08:00
Akash Levy 86d321a306 Undo blif frontend stuff 2024-11-12 01:30:06 -08:00
Akash Levy 83234d24f7 Switch from Synopsys register naming to preserve 2024-11-11 17:06:56 -08:00
Akash Levy 894c9816d3 Improve naming: big fix 2024-11-11 17:06:11 -08:00
Akash Levy fa50434708
Merge branch 'YosysHQ:main' into main 2024-11-08 14:10:24 -08:00
Miodrag Milanovic df391f5816 verific: fix blackbox regression and add test case 2024-11-08 14:57:04 +01:00
Akash Levy 1cba744712 Update 2024-11-04 17:01:41 -08:00
Krystine Sherwin ee73a91f44
Remove references to ilang 2024-11-05 12:36:31 +13:00
George Rennie dbfca1bdff frontends/ast.cc: special-case zero width strings as "\0" 
* Fixes #4696
 2024-11-01 17:19:28 +01:00
Alain Dargelas 615f523ef4 pass no_split_complex_ports to hierarchy command 2024-10-29 13:37:03 -07:00
Akash Levy 5e606722e3 Get autoidx reset working 2024-10-28 16:30:47 -07:00
Akash Levy 038c562493 VHDL support fix 2024-10-25 11:32:52 -07:00
Akash Levy 8e667e2e9f Add documentation for VHDL library directory 2024-10-23 23:53:21 -07:00
Akash Levy 17c8567b02 Really tiny fixes 2024-10-23 22:03:00 -07:00
Akash Levy 3d127dff4a Add set VHDL default library path 2024-10-21 01:22:56 -07:00
Akash Levy c94eac14b9 Remove GHDL and add mixed SV-VHDL support 2024-10-20 23:29:33 -07:00
Akash Levy e2659247fc Verific UPF eval working 2024-10-17 04:40:38 -07:00
Akash Levy cafd4cbbe8
Merge branch 'YosysHQ:main' into main 2024-10-15 06:43:06 -07:00
Emil J. Tywoniak 81bbde62ca verilog_parser: silence yynerrs warning 2024-10-15 08:32:55 -04:00
Akash Levy 469f5a707a
Merge branch 'YosysHQ:main' into main 2024-10-14 11:21:54 -07:00
Emil J caf56ca3e8
Merge pull request #4516 from YosysHQ/emil/src-attribute-std-string-wip 
Represent string constants as strings
 2024-10-14 06:42:54 -07:00
Emil J. Tywoniak 785bd44da7 rtlil: represent Const strings as std::string 2024-10-14 06:28:12 +02:00
Miodrag Milanovic 8d2b63bb8a Set VHDL assert condition initial state if fed by FF 2024-10-11 16:32:21 +02:00
Akash Levy 48cb802599 Undo bound removal 2024-10-10 13:34:18 -07:00
Akash Levy fdc4c54c66
Merge branch 'YosysHQ:main' into main 2024-10-07 07:27:27 -10:00
Martin Povišer 0aab8b4158
Merge pull request #4605 from povik/liberty-unit-delay 
read_liberty: Optionally import unit delay arcs
 2024-10-07 16:11:51 +02:00
Martin Povišer 74e92d10e8
Merge pull request #4593 from povik/aiger2 
New aiger backend
 2024-10-07 16:11:25 +02:00
Martin Povišer 7989d53c58 read_xaiger2: Add help 2024-10-07 14:19:49 +02:00
Martin Povišer f44a418212 read_xaiger2: Add casts to silence warnings 2024-10-07 12:27:54 +02:00
Martin Povišer 8d12492610 read_xaiger2: Fix detecting the end of extensions 2024-10-07 12:03:48 +02:00
Martin Povišer 2b1b5652f1 Adjust `read_xaiger2` prints 2024-10-07 12:03:48 +02:00
Akash Levy f76cb43ac7 Add bundle support 2024-10-05 01:35:03 -10:00
Akash Levy dd487ca8a1 Updating Yosys 2024-10-03 01:46:09 -07:00
Akash Levy 5038bfa2af Fix minor whitespace thing 2024-10-03 00:29:16 -07:00
Akash Levy ec296736f5 Simplify multiport 2024-10-02 22:19:09 -07:00
Akash Levy 400ae0bbab Prune RAM dimensions 2024-10-02 03:44:57 -07:00
Akash Levy 8bf86e8d1f Undo 2024-10-02 03:30:30 -07:00
Akash Levy ff0fd570d8 Revert mem but fix Verific frontend to remove ugliness 2024-10-02 01:17:01 -07:00
Akash Levy ee0b083a1e
Merge branch 'YosysHQ:main' into main 2024-09-30 02:43:09 -07:00
rherveille ce7db661a8
Added cast to type support (#4284) 2024-09-29 17:03:01 -04:00
Akash Levy 0610d6ccc2 Smallfix to get GHDL working 2024-09-27 06:38:42 -07:00
Akash Levy bb2cdd61fe Fix GHDL and bump yosys-slang 2024-09-27 04:43:59 -07:00
Akash Levy 5a27db1463 Smallfix 2024-09-27 03:31:30 -07:00
Akash Levy f6d577aed1 Fix GHDL support 2024-09-27 03:14:15 -07:00
Akash Levy 0fd6e29e8e Fixups 2024-09-23 04:25:10 -07:00
Akash Levy 0b8d951493 Add synopsys VHDL libs by default in GHDL 2024-09-23 04:05:27 -07:00
Akash Levy 69bf7875dd Small edits 2024-09-22 07:52:58 -07:00
Akash Levy d655766c49 Smallfix 2024-09-22 06:57:28 -07:00
Akash Levy 89f9035a98 Fix VHDL checking 2024-09-22 06:45:47 -07:00
Akash Levy 7d5dac7255 More apt location for whereami 2024-09-22 06:02:20 -07:00
Akash Levy f1ab51ce5b Clean up and remove hdl_file_sort 2024-09-22 05:58:17 -07:00
Akash Levy f0b1d2cac5 Small changes 2024-09-22 01:11:26 -07:00
Akash Levy 4cf9bb86ca Smallfix 2024-09-19 01:04:29 -07:00
Akash Levy 7988a61f8c Use enable debug and switch order of Verific opt passes 2024-09-19 00:48:31 -07:00
Akash Levy 2d139c8735 Smallfix to remove top/bottom-bound attributes 2024-09-18 14:46:13 -07:00
Martin Povišer f168b2f4b1 read_xaiger2: Update box handling 2024-09-18 16:55:02 +02:00
Martin Povišer 1ab7f29933 Start read_xaiger2 -sc_mapping 2024-09-18 16:42:56 +02:00
Martin Povišer 4976abb867 read_liberty: Optionally import unit delay arcs 2024-09-18 16:17:03 +02:00
Akash Levy 44789c9f6c Move ram opt around 2024-09-16 18:56:48 -07:00
Akash Levy 285c8a3f66
Merge branch 'YosysHQ:main' into main 2024-09-12 11:14:15 -07:00
N. Engelhardt c8b42b7d48
Merge pull request #4538 from RCoeurjoly/verific_bounds 2024-09-12 13:04:04 +02:00
Akash Levy 985de62d3c
Merge branch 'YosysHQ:main' into main 2024-09-11 16:01:37 -07:00
Emil J. Tywoniak 1372c47036 internal_stats: astnode (sizeof) 2024-09-11 11:34:20 +02:00
Roland Coeurjoly bdc43c6592 Add left and right bound properties to wire. Add test. Fix printing 
for signed attributes

Co-authored-by: N. Engelhardt <nak@yosyshq.com>
Co-authored-by: Roland Coeurjoly <rolandcoeurjoly@gmail.com>
 2024-09-10 12:52:42 +02:00
Akash Levy ce95ec1f9e Add VHDL support via GHDL call 2024-09-05 13:24:38 -07:00
Akash Levy 57446f3f93
Merge branch 'YosysHQ:main' into master 2024-08-21 18:52:38 -07:00
Akash Levy 6e46a56720 Fix Verific warning 2024-08-21 16:55:44 -07:00
Roland Coeurjoly 27c1432253 Remove log 2024-08-21 14:28:42 +01:00
Roland Coeurjoly 91e3773b51 Ensure signed constants are correctly parsed, represented, and exported in RTLIL. Add a test to check parsing and exporting 2024-08-21 14:28:42 +01:00
Akash Levy dba9a26cf3 Make default macros optional 2024-08-21 00:50:10 -07:00
Akash Levy 34e5bc1129
Merge branch 'YosysHQ:main' into master 2024-08-14 16:56:53 -07:00
Martin Povišer ab5d6b06b4 read_liberty: Fix omitted helper change 2024-08-13 20:12:38 +02:00
Martin Povišer 309d80885b read_liberty: Use available gate creation helpers 2024-08-13 18:47:36 +02:00
Martin Povišer 3057c13a66 Improve libparse encapsulation 2024-08-13 18:47:36 +02:00
Akash Levy 68b3ad4bd3 Display resource sharing count 2024-08-06 02:27:09 -07:00
Akash Levy c0af4604bc Update Yosys 2024-07-30 16:55:18 -07:00
Miodrag Milanović 3e14e67374
Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase 
VHDL is case insensitive, make sure netlist name is proper
 2024-07-29 16:44:13 +02:00
Miodrag Milanovic 405897a971 Update top value that is returned back to hierarchy pass 2024-07-29 15:50:38 +02:00
Akash Levy f790b75c19 Don't preserve user nets and update Verific tree balancing 2024-07-25 06:01:06 -07:00
Miodrag Milanovic 9566709426 Initialize extensions when verific pass is registered 2024-07-25 11:25:17 +02:00
Akash Levy f1114cc98c Simplify ignores 2024-07-24 02:14:11 -07:00
Akash Levy ebc9f96f85
Merge branch 'YosysHQ:main' into master 2024-07-23 15:01:54 -07:00
Miodrag Milanovic c94aa719d9 VHDL is case insensitive, make sure netlist name is proper 2024-07-18 16:56:52 +02:00
Emil J. Tywoniak 72a0380da8 ast: don't suggest use in external projects 2024-07-18 16:37:14 +02:00
Akash Levy f18ddb5db2 Remove wide operator control 2024-07-10 12:53:59 -07:00
Akash Levy 8f4b66ae77 Set db_infer_wide_operators externally 2024-07-08 08:32:34 -07:00
Akash Levy 70016a08b8 Disable debug 2024-07-03 06:55:53 -07:00
Akash Levy 30241e07eb Fix segfault 2024-07-03 02:29:48 -07:00
Akash Levy fcd073ab51 Smallfix 2024-07-02 15:13:58 -07:00
Akash Levy 0596766cbd Merge upstream yosys changes 2024-07-01 18:33:38 -07:00
Akash Levy dec43679be See if this fixes issues on Innatera design 2024-06-28 03:13:38 -07:00
gatecat 22d8df1e7e liberty: Support for IO liberty files for verification 
Signed-off-by: gatecat <gatecat@ds0.me>
 2024-06-19 21:12:42 +02:00
Akash Levy 719bbd7523 Improve SCC reporting 2024-06-17 14:18:41 -07:00
Miodrag Milanovic dfde792288 Refactored import code 2024-06-17 14:49:58 +02:00
Miodrag Milanovic 19da7f7d59 Update makefile to make options uniform 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0f3f731254 Handle -work for vhdl, and clean messages 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 0a81c8e161 Import all modules from all libraries when when needed 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7c3094633d Compile with hier_tree separate SV and VHDL as well 2024-06-17 13:29:11 +02:00
Miodrag Milanovic e2e189647f Cleanup 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 7bec332b68 SV + VHDL with RTL support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 25d50bb2af VHDL only build support 2024-06-17 13:29:11 +02:00
Miodrag Milanovic 54bf9ccf06 Add initial support for Verific without additional YosysHQ patch 2024-06-17 13:29:11 +02:00
Akash Levy a0c0384683 Preserve instances 2024-06-16 20:20:10 -07:00
Akash Levy e23e33441f Update yosys from upstream 2024-06-15 14:23:24 -07:00
Akash Levy fce46d2a53 Add better Yosys/Verific name aliasing and reenable dffe opt 2024-06-15 14:18:33 -07:00
Akash Levy 2337d97977 Sub1 fix 2024-06-13 15:33:17 -07:00
Akash Levy ac0a9e7366 Updates 2024-06-10 20:52:11 -07:00
Akash Levy b9b776d211 Update for no preservation of user nets 2024-06-10 20:33:05 -07:00
Martin Povišer b593f5c01c Update the overview comment in `ast.h` 2024-06-10 16:38:39 +02:00
Akash Levy d930310599 Enable more updates 2024-06-09 13:54:34 -07:00
Mike Inouye b0ab1cf8c3 Fix memory leak in verific file parsing. 
Signed-off-by: Mike Inouye <mikeinouye@google.com>
 2024-06-07 22:51:28 +00:00
Akash Levy 8499d31cf2 Revert veri_break_loops setting 2024-06-07 00:09:01 -07:00
Akash Levy c8f7441a4a Fix skip default value 2024-06-05 09:33:03 -07:00
Akash Levy c59a997255 Ignore files properly 2024-06-05 07:53:21 -07:00
Akash Levy 4d44099d09 Support for ignoring translate_off and ignoring files 2024-06-05 05:00:05 -07:00
Akash Levy 5dc62bec0b Support .inc files and readmemh missing file 2024-06-03 20:05:30 -07:00
Akash Levy 92e44cc9a3 Minor fix to ignore files 2024-06-03 18:17:50 -07:00
Akash Levy 4339b3681a Elaborate top level modules undo 2024-06-03 16:17:51 -07:00
Akash Levy a692bf17d7 Improper ignore translates 2024-06-03 11:23:16 -07:00
Akash Levy 783c0a593a Actually optimize with Verific now 2024-06-03 04:55:47 -07:00
Akash Levy 4475b50ffa Undo some ugly stuff and make more attempted fixes 2024-06-02 23:33:23 -07:00
Akash Levy 2585636d18 Use ability to get/set IMPORT runtime flags 2024-06-02 22:24:29 -07:00
Akash Levy 28a03380b7 Priority selector fixes (opt order), relaxed checking, warning if using Yosys case statements 2024-06-02 18:45:31 -07:00
Akash Levy 85cbd05bb1 Update some runtime flags to fix some potential issues 2024-06-02 01:12:43 -07:00
Akash Levy 5bc23b272a Add blackboxes a little later and use ignore files rather than ignore modules 2024-05-30 14:17:10 -07:00
Akash Levy 8b93aa10cb Add leakage power unit support 2024-05-29 23:43:47 -07:00
Akash Levy a55a4d461e Infer wide operators pre elaboration (post does not work as well!) 2024-05-28 04:39:29 -07:00
Akash Levy 4062825a9e Disable Liberty support, add blackbox Verilog module, and add attribute parsing into Yosys Liberty parser 2024-05-28 01:47:46 -07:00
Akash Levy b90c20cd14 Update Verific, add opt to hierarchy pass, make opt run a bunch of Verific optimizations, update some Verific runtime flags 2024-05-27 21:56:08 -07:00
Akash Levy a98fcbd48b Revert Verific flags 2024-05-25 23:21:31 -07:00
Akash Levy 60ce37c2bd Don't reenable verific, move to c_cpp_properties.json in .vscode 2024-05-24 01:49:54 -07:00
Akash Levy 22bdf4035a Verific to handle all RAMs 2024-05-24 01:08:37 -07:00
Akash Levy 6300c491ea Update Yosys runtime flags for Verific to remove multi-port memory support 2024-05-24 00:26:37 -07:00
Akash Levy 66eabb1d2c Define SYNTH and OVL_SVA by default 2024-05-23 21:05:57 -07:00
Akash Levy 187737b86a Don't adjust naming on imported cells. Add $ for each pass 2024-05-19 15:02:40 -07:00
Akash Levy 60e598b9c8 Define SYNTHESIS earlier and in both, support ignored module specification 2024-05-17 04:46:28 -07:00
Akash Levy 375f73bbce Update for Amba support 2024-05-15 15:37:14 -07:00
Akash Levy ed42470d45 Move ignore translate up here and update verificc 2024-05-14 16:02:33 -07:00
Akash Levy 81b542fd31 Updated to support Amba comments and .h files 2024-05-14 13:25:43 -07:00
Akash Levy 667c3375e8 Macro defines don't pass or succeed the same way 2024-05-13 15:53:54 -07:00
Akash Levy fb182d10d6 Update formats to include .svh 2024-05-13 00:00:49 -07:00
Akash Levy ba5b12ae0c Don't include source in name 2024-05-11 23:14:39 -07:00
Akash Levy 36f9c50c03 Add mode for nested capital F file 2024-05-11 12:53:33 -07:00
Akash Levy a7e1dcef12 Move register file to after registering directories, also rename to AUTO-DISCOVER 2024-05-10 12:44:36 -07:00
Akash Levy fb55287a3b Add SVP extension, log auto-discovery, support gzip in verific 2024-05-10 11:09:22 -07:00
Akash Levy c7f66737aa Fix Yosys to allow SV again 2024-05-09 06:36:02 -07:00
Akash Levy da8c1955af Updates from YosysHQ 2024-05-09 05:10:44 -07:00
Akash Levy 8841cc4d76 Copy all info from .f file to hdl_file_sort for better auto-discovery 2024-05-09 04:54:57 -07:00
Akash Levy b5af9b9a8a Fix SystemVerilog support for .v files 2024-05-09 04:54:00 -07:00
Miodrag Milanović 1a54e8d47b
Merge pull request #4379 from QuantamHD/fix_verific 
frontend: Fixes verific import around range order
 2024-05-09 11:52:34 +02:00
Ethan Mahintorabi 82a4a87c97
Fixes error with vector indicies of the form [2:7] [-12:7] 
Make sure that we correctly adjust the value to align it to a zero
indexed list with lsb = 0

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 20:29:47 +00:00
Akash Levy 47b6738124 Add -auto_discover to import 2024-05-08 04:21:30 -07:00
Akash Levy 2e21078a83
Merge branch 'YosysHQ:main' into master 2024-05-07 18:21:19 -07:00
Ethan Mahintorabi c039da2ec1
renames variables for more code clairty 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:09:52 +00:00
Ethan Mahintorabi a2c1b268d9
frontend: Fixes verific import around range order 
Test Case
```
module packed_dimensions_range_ordering (
    input  wire [0:4-1] in,
    output wire [4-1:0] out
);
  assign out = in;
endmodule : packed_dimensions_range_ordering

module instanciates_packed_dimensions_range_ordering (
    input  wire [4-1:0] in,
    output wire [4-1:0] out
);
  packed_dimensions_range_ordering U0 (
      .in (in),
      .out(out)
  );
endmodule : instanciates_packed_dimensions_range_ordering
```

```
// with verific, does not pass formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = { in[0], in[1], in[2], in[3] };
endmodule

// with surelog, passes formal
module instanciates_packed_dimensions_range_ordering(in, out);
  input [3:0] in;
  wire [3:0] in;
  output [3:0] out;
  wire [3:0] out;

  assign out = in;
endmodule
```

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-05-08 01:00:06 +00:00
Krystine Sherwin df95ea824b read_verilog: Add missing defaults for flags 
Fix for YosysHQ/sby#103
 2024-05-07 20:25:36 +02:00
Akash Levy 8c330c0e4b
Merge branch 'YosysHQ:main' into master 2024-04-29 22:22:47 -07:00
George Rennie 4e6deb53b6 read_aiger: Fix incorrect read of binary Aiger without outputs 
* Also makes all ascii parsing finish reading lines and adds a small
  test
 2024-04-29 14:06:58 +01:00
Akash Levy 45b723d6f3
Merge branch 'YosysHQ:main' into master 2024-04-25 06:24:57 -07:00
KrystalDelusion c3ae33da33
Merge pull request #4285 from YosysHQ/typo_fixup 
Typo fixing
 2024-04-25 09:54:48 +12:00
Akash Levy 3945e6ecff
Merge branch 'YosysHQ:main' into master 2024-04-16 10:59:45 -07:00
Miodrag Milanovic af94123730 verific: expose library name as module attribute 2024-04-15 17:01:07 +02:00
Akash Levy 6a3bb58d5d Updates from yosys 2024-04-14 18:53:44 -07:00
N. Engelhardt 3d5e23e585
Merge pull request #4302 from YosysHQ/vhdl_2019 
Verific support for VHDL 2019
 2024-04-09 18:25:05 +02:00
N. Engelhardt 18afa36acd
Merge pull request #4273 from YosysHQ/vhdl_params 
verific: Improve import VHDL constants
 2024-04-09 18:01:41 +02:00
Akash Levy 29e9d3ea92 Updates for hiding verific 2024-04-09 07:16:22 -07:00
akash 840cdb415b Update Verific, add to gitmodules, remove unused/GPL features from Makefile 2024-04-08 12:36:08 -07:00
Akash Levy e3f633fae6
Merge branch 'YosysHQ:main' into master 2024-04-08 12:26:40 -07:00
Catherine a5441bc00c fmt: `FmtPart::{STRING→LITERAL},{CHARACTER→STRING}`. 
Before this commit, the `STRING` variant inserted a literal string;
the `CHARACTER` variant inserted a string. This commit renames them
to `LITERAL` and `STRING` respectively.
 2024-04-02 12:13:22 +02:00
Miodrag Milanovic f536de0e0e Verific support for VHDL 2019 2024-03-28 13:21:55 +01:00
Akash Levy dd35d2da23 Modifications 2024-03-21 11:31:43 -07:00
Miodrag Milanovic 4367e176fb code split and cleanup 2024-03-19 09:15:04 +01:00
Miodrag Milanovic 9eebc80170 handle standard types 2024-03-18 10:35:01 +01:00
Krystine Sherwin 3eeefd23e3
Typo fixup(s) 2024-03-18 11:09:23 +13:00
Miodrag Milanovic 7c09fa572e real number handling and default to string 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 4279cea33a improve handling VHDL constants 2024-03-14 10:37:56 +01:00
Miodrag Milanovic 858eae5572 verific_const: convert VHDL values to RTLIL consts 2024-03-14 10:37:56 +01:00
Martin Povišer b16f4900fd ast/simplify: Interpret hdlname w/o expecting backslash 2024-02-13 21:38:41 +01:00
Catherine d8ce26a5ba read_verilog: correctly format `hdlname` attribute value. 
The leading slash is not a part of the attribute as it only concerns
public values.
 2024-02-13 18:41:53 +00:00
Miodrag Milanovic ae7daf99f4 Verific: Add attributes to module instantiation 2024-02-12 09:53:47 +01:00
Dag Lem f09ea16bd1 Resolve struct member multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem 03f35c3def Resolve multiple dimensions defined in stages with typedef 2024-02-11 11:26:52 -05:00
Dag Lem e0d3977e19 Add support for $dimensions and $unpacked_dimensions 2024-02-11 11:26:52 -05:00
Dag Lem 2125357e76 Add support for $increment 2024-02-11 11:26:52 -05:00
Dag Lem 88d9e213cb Decoding of a few more AST nodes in dumpVlog 2024-02-11 11:26:52 -05:00
Dag Lem 39fea32c6e Add support for packed multidimensional arrays 
* Generalization of dimensions metadata (also simplifies $size et al.)
* Parsing and elaboration of multidimensional packed ranges
 2024-02-11 11:26:52 -05:00
Catherine 1236bb65b6 read_verilog: don't include empty `opt_sva_label` in span. 
Consider this SystemVerilog file:

    module top(...);
      input clk;
      input [7:0] data;
      input ack;

      always @(posedge clk)
        if (ack) begin
          assert(data != 8'h0a);
        end
    endmodule

Before this commit, the span for the assert was:

        if (ack) begin>
          assert(data != 8'h0a)<;

After this commit, the span for the assert is:

        if (ack) begin
          >assert(data != 8'h0a)<;

This helps editor integrations that only look at the beginning
of the span.
 2024-02-08 14:25:35 +00:00
Miodrag Milanović 5d3e4c5c7a
Merge pull request #4182 from QuantamHD/fix_aldff 
verific: Improves aldff inference in verific importer
 2024-02-06 08:19:43 +01:00
N. Engelhardt 2422dd6845
Merge pull request #4153 from Coloquinte/blif_delay_constraints 
Issue a warning instead of a syntax error for blif delay constraints
 2024-02-05 15:14:05 +01:00
Ethan Mahintorabi ff578ecabd
fix formatting 
Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:23:04 +00:00
Ethan Mahintorabi bc66dfd9ea
verific: Fixes incorrect aldff inference in verific importer 
The following SV module at HEAD imported with verific,

```systemverilog
    module my_module(
      input logic [4:0] a,
      input logic clk,
      input logic enable,
      output logic [4:0] z
    );

    reg [4:0] pipeline_register;
    always @(posedge clk) begin
      pipeline_register <= enable ? a : pipeline_register;
    end
    assign z = pipeline_register;

    endmodule : my_module

```

results in the following output verilog

```systemverilog
/* Generated by 0.36 */

(* top =  1  *)
(* hdlname = "my_module" *)
(* src = "/tmp/temp_directory_zTwd0l/my_input.v:2.12-2.21" *)
module my_module(clk, enable, a, z);
  wire [4:0] _0_;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:3.25-3.26" *)
  input [4:0] a;
  wire [4:0] a;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:4.19-4.22" *)
  input clk;
  wire clk;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:5.19-5.25" *)
  input enable;
  wire enable;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:6.26-6.27" *)
  output [4:0] z;
  wire [4:0] z;
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:10.12-12.8" *)
  \$aldff  #(
    .ALOAD_POLARITY(32'd1),
    .CLK_POLARITY(32'd1),
    .WIDTH(32'd5)
  ) _1_ (
    .AD(5'hxx),
    .ALOAD(1'h0),
    .CLK(clk),
    .D(_0_),
    .Q(z)
  );
  (* src = "/tmp/temp_directory_zTwd0l/my_input.v:11.28-11.58" *)
  \$mux  #(
    .WIDTH(32'd5)
  ) _2_ (
    .A(z),
    .B(a),
    .S(enable),
    .Y(_0_)
  );
endmodule
```

Yosys is incorrectly infering aldffs due to an incorrect conversion
of logical 1 and 0 SigBits.

My PR unifies the conversion of Verific::Net objects into SigBits using
Yosys' internal representation of special signals like 0,1,x,z. After
my PR these signals are correctly converted into DFFs.

Signed-off-by: Ethan Mahintorabi <ethanmoon@google.com>
 2024-02-05 07:10:25 +00:00
Catherine c7bf0e3b8f Add new `$check` cell to represent assertions with a message. 2024-02-01 20:10:39 +01:00
Miodrag Milanovic db1de5fe5d verific: add option to skip simplifying complex ports 2024-01-30 16:33:44 +01:00
Gabriel Gouvine c634d59c18 Issue a warning instead of a syntax error for blif delay constraints 2024-01-23 16:25:16 +00:00
Miodrag Milanovic 1764c0ee3c Fix verific clocking when no driver exist 2024-01-18 08:47:04 +01:00
Martin Povišer 149bcd88ad
Merge pull request #4026 from uis246/fix-format 
Fix printf formats
 2024-01-15 16:04:11 +01:00
uis 5902b2826d Fix printf formats 2024-01-15 12:07:54 +01:00
Catherine 1159e48721 write_verilog: emit `initial $display` correctly. 2024-01-11 13:13:04 +01:00
Dag Lem 3ed9030eb4 Optionally suppress output from display system tasks in read_verilog 2024-01-11 13:12:53 +01:00
Jannis Harder 510d137996 fmt: Allow non-constant $display calls in initial blocks 
These are useful for formal verification with SBY where they can be used
to display solver chosen `rand const reg` signals and signals derived
from those.

The previous error message for non-constant initial $display statements
is downgraded to a log message. Constant initial $display statements
will be shown both during elaboration and become part of the RTLIL so
that the `sim` output is complete.
 2024-01-11 13:01:28 +01:00
Dag Lem 23cd23efc5 Simplify and correct AST for array slice assignment 
Corrects sign extension of the right hand side, and hopefully
makes the code simpler to understand.

Fixes #4064
 2024-01-10 21:15:00 +01:00
Dag Lem 1a2b4759e8 Assign from rvalue via temporary register in nowrshmsk CASE 
Avoid repeating complex rvalue expressions for each condition.
 2024-01-10 20:40:01 +01:00
Dag Lem 2cab4ff173 Correction and optimization of nowrshmsk 
This makes tests/verilog/dynamic_range_lhs.v pass, after ensuring that
nowrshmsk is actually tested.

Stride is extracted from indexing of two-dimensional packed arrays and
variable slices on the form dst[i*stride +: width] = src, and is used
to optimize the generated CASE block.

Also uses less confusing variable names for indexing of lhs wires.
 2024-01-10 20:28:36 +01:00
Martin Povišer 6f7f71fe03 read_blif: Represent sequential elements with gate cells 
When reading the BLIF input, represent the native sequential elements
with fine-grained cells like `$_FF_` instead of the coarse-grained cells
like `$ff` which we were using up to now.

There are two reasons for this:

 * The sequential elements in BLIF are always single-bit, so the gate
   cells are a better fit.

 * This makes it symmetrical to the BLIF backend which only understands
   the fine-grained cells, and only translates those to the native BLIF
   features.
 2024-01-09 19:31:44 +01:00
Dag Lem 1bbea13f80 Correct hierarchical path names for structs and unions 2024-01-04 17:22:07 +01:00
Martin Povišer 320e75a3e3
Merge pull request #4065 from daglem/fix-AST_SHIFT-AST_SHIFTX 
Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX
 2023-12-12 11:47:29 +01:00
Dag Lem 655921e851 Uncloak array expressions generated by read_verilog -dump_vlog2 
Explicit conversion of AST_TO_SIGNED, AST_TO_UNSIGNED, and AST_CAST_SIZE
makes it possible to reason about simplified array expressions.
 2023-12-11 19:12:35 +01:00
Dag Lem cda470d63e Respect the sign of the right operand of AST_SHIFT and AST_SHIFTX 
The $shift and $shiftx cells perform a left logical shift if the second
operand is negative. This change passes the sign of the second operand
of AST_SHIFT and AST_SHIFTX into $shift and $shiftx cells, respectively.
 2023-12-11 18:58:34 +01:00
Miodrag Milanovic 96fecf0716 Revert "Add attributes to module instantiation" 
This reverts commit 8f207eed1b.
 2023-12-04 16:37:01 +01:00
Miodrag Milanovic 8f207eed1b Add attributes to module instantiation 2023-11-23 11:01:49 +01:00
N. Engelhardt 5fb1264db5 verific: don't try to import attributes from nullptr 2023-11-14 15:05:24 +01:00
N. Engelhardt 93a426cbbf
Merge pull request #4008 from nakengelhardt/mem_libmap_data_attr 
memory_libmap: look for ram_style attributes on surrounding signals
 2023-11-06 16:25:38 +01:00
Miodrag Milanovic f06d56d224 Handling non-existing location in verific logs 2023-11-03 08:06:16 +01:00
Miodrag Milanovic 4eb18e1f07 change verific log callback api 2023-11-01 08:13:27 +01:00
N. Engelhardt 833b67af80 verific: import attributes on ports 
Co-authored-by: Miodrag Milanović <mmicko@gmail.com>
 2023-10-20 18:31:41 +02:00
Miodrag Milanovic d473a207a1 Preserve VHDL architecture name in attribute 2023-10-12 09:17:06 +02:00
Jannis Harder 4ed708836a verific: Use CellBaseName to identify top modules 2023-10-10 11:51:16 +02:00
Martin Povišer 8367f06188 ast/simplify: Remove unused in_param code 2023-10-05 22:42:36 -04:00
Miodrag Milanović a54e6f2d1f
Merge pull request #3984 from YosysHQ/module_hdlname 
verific: save original module name
 2023-10-05 19:41:00 +02:00
Jannis Harder 47a4b790f8 verific: Pass top modules to static elaboration when using hierarchy 2023-10-05 16:51:49 +02:00
Jannis Harder 23b9e61c47 verific: Pass list of top modules to static elaboration 2023-10-05 16:51:49 +02:00
Miodrag Milanovic 268fe92d22 verific: save original module name 2023-10-05 11:22:40 +02:00