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systemlib
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aligned pdf hardcopy colors to xschem light colorscheme, pdf and svg exports use the enable_layer[] array to display/hide layers as does draw().
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2020-08-30 10:38:29 +02:00 |
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utile
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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Makefile.in
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add sample file for custom menu additions
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2021-01-05 15:55:12 +01:00 |
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actions.c
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added "auto join/trim wires" menu option since now the trim operation is doing fast even on big designs
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2021-01-02 03:24:26 +01:00 |
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add_custom_menu.tcl
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add sample file for custom menu additions
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2021-01-05 15:55:12 +01:00 |
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break.awk
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added flatten_savenodes.awk for flattening in-subcircuit .save instructions
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2020-12-14 16:31:20 +01:00 |
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callback.c
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more flexibility in constrained move operations (draw wires, lines, copy/move), pressing h/v again toggles constrained / unsonstrained move
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2021-01-05 01:24:45 +01:00 |
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change_index.tcl
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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change_ref.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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check.c
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prepare for delete connection implementation
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2021-01-03 00:06:41 +01:00 |
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clip.c
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"lazy man" (good enough for schematics) aproximated polygon clipping using the underlying xorg 16 bit integer poly clipping engine, by projecting outer vertices to the 16 bit signed coordinate system edges
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2020-12-05 13:58:44 +01:00 |
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convert_to_verilog2001.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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draw.c
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Add Shift-Delete command that selects all nets/labels/probes physically attached to current selected wire segment/label/pin/probe
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2021-01-02 18:56:42 +01:00 |
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editprop.c
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correctly unhilight instances after changing net labels
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2021-01-06 13:29:14 +01:00 |
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exp.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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expandlabel.y
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fix unfreed pointer in get_logic_value()
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2020-12-28 12:29:57 +01:00 |
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findnet.c
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eliminated some global vars
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2020-12-23 05:07:39 +01:00 |
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flatten.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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flatten_savenodes.awk
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fixed typo in spice.awk
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2020-12-20 12:46:00 +01:00 |
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flatten_tedax.awk
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fix mapping issue in hiertEDAx code. Thanks to Hannu for pointing it out. Allow newlines in (quoted) long vector labels, like: "AAA,BBB,\nCCC,DDD,EEE"
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2020-11-30 21:01:33 +01:00 |
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font.c
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more globals into xctx context struct
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2020-12-02 15:10:47 +01:00 |
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get_malloc_id.awk
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pass name and symname to tcl_hook, add @symname_ext in print_spice_element
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2020-10-14 21:04:45 +02:00 |
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globals.c
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more flexibility in constrained move operations (draw wires, lines, copy/move), pressing h/v again toggles constrained / unsonstrained move
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2021-01-05 01:24:45 +01:00 |
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gschemtoxschem.awk
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fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli
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2020-12-17 03:48:34 +01:00 |
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gtkwave_server.tcl
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add gtkwave_server.tcl hook for gtkwave to listen to a tcp port
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2020-09-24 02:28:00 +02:00 |
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hash_iterator.c
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Add Shift-Delete command that selects all nets/labels/probes physically attached to current selected wire segment/label/pin/probe
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2021-01-02 18:56:42 +01:00 |
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herculestospice.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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hilight.c
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various fixes for corner cases where changing labels of hilight nets (update inst[].color), update symbol bboxes when toggling show_pin_net_names
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2021-01-06 05:47:05 +01:00 |
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hspice_backannotate.tcl
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ngspice_probe type set from "probe" to "ngprobe" to avoid clashes
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2021-01-02 19:44:01 +01:00 |
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icon.c
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better xschem icon: added shapemask for "transparent" background
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2020-11-10 13:17:25 +01:00 |
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icon.xpm
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better xschem icon: added shapemask for "transparent" background
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2020-11-10 13:17:25 +01:00 |
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import_opus_symbols.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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in_memory_undo.c
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make in_memory_undo work again (some variable changes missing after code refactoring)
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2021-01-02 02:05:13 +01:00 |
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keys.help
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documentation updates
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2021-01-02 22:18:46 +01:00 |
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label_compactor.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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main.c
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undo data structures into xctx context
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2020-12-04 00:30:13 +01:00 |
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make_edif.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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make_sch_from_cadence_pin.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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make_sch_from_spice.awk
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fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli
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2020-12-17 03:48:34 +01:00 |
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make_sch_from_vhdl.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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make_sym.awk
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fix make_sym.awk duplicating name= attribute in generated symbol
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2020-12-29 14:14:32 +01:00 |
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make_vhdl_from_spice.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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move.c
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finalizing "select nets up to junctions"
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2021-01-03 01:26:54 +01:00 |
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netlist.c
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prepare(3) for delete connection implementation
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2021-01-03 00:08:43 +01:00 |
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netlist_compactor.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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ngspice_backannotate.tcl
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fixes and comments in annotation schematic examples
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2020-12-29 23:17:00 +01:00 |
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node_hash.c
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hash_hi() made faster by caching sch_path_hash[]
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2021-01-02 01:55:01 +01:00 |
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options.c
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postscript fonts in ps/pdf export
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2020-12-16 18:30:33 +01:00 |
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order_labels.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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parse_synopsys_vhdl.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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parselabel.l
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allow ! in net names, it got deleted after the parselabel rework.
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2020-12-13 20:26:39 +01:00 |
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paste.c
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saving to file made 4x faster, this implies less latency due to undo buffer savings on freaking big schematics.
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2021-01-06 03:01:14 +01:00 |
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psprint.c
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add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports
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2021-01-06 00:12:04 +01:00 |
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rawtovcd.c
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code refactoring (global context in Xschem_ctx), "New Schematic" or "New Symbol" will set netlist_type to "spice" or "symbol" respectively
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2020-10-12 13:13:31 +02:00 |
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reduce_even_odd_array_labels.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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rescale.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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resources.tcl
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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save.c
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saving to file made 4x faster, this implies less latency due to undo buffer savings on freaking big schematics.
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2021-01-06 03:01:14 +01:00 |
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scheduler.c
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various fixes for corner cases where changing labels of hilight nets (update inst[].color), update symbol bboxes when toggling show_pin_net_names
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2021-01-06 05:47:05 +01:00 |
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select.c
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saving to file made 4x faster, this implies less latency due to undo buffer savings on freaking big schematics.
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2021-01-06 03:01:14 +01:00 |
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sort_labels.awk
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fix a regression in sort_labels.awk after moving tmpfile to /tmp; added oldvalue (for simulation) in hilight hash table
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2020-12-26 23:53:26 +01:00 |
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spice.awk
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fixed typo in spice.awk
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2020-12-20 12:46:00 +01:00 |
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spice_netlist.c
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hash_hi() made faster by caching sch_path_hash[]
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2021-01-02 01:55:01 +01:00 |
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store.c
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each schematic windows has its own "current later" (rectcolor)
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2020-12-06 16:40:08 +01:00 |
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supergrep.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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svgdraw.c
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Add Shift-Delete command that selects all nets/labels/probes physically attached to current selected wire segment/label/pin/probe
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2021-01-02 18:56:42 +01:00 |
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symgen.awk
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fix regression due to r1395, updated Changelog, fix set initial window size when doing ps/pdf export from cli
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2020-12-17 03:48:34 +01:00 |
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tedax.awk
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hiertEDAx: don\t split on escaped white space. test schematic with weird instance/net names
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2020-11-24 15:25:37 +01:00 |
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tedax_netlist.c
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hash_hi() made faster by caching sch_path_hash[]
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2021-01-02 01:55:01 +01:00 |
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token.c
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saving to file made 4x faster, this implies less latency due to undo buffer savings on freaking big schematics.
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2021-01-06 03:01:14 +01:00 |
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track_memory.awk
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fix unfreed pointer in get_logic_value()
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2020-12-28 12:29:57 +01:00 |
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traduci.awk
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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verilog.awk
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better node multiplicity detection in spice and verilog awk netlist post-processors (\?-?[0-9]+)
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2020-10-16 00:13:39 +02:00 |
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verilog_netlist.c
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hash_hi() made faster by caching sch_path_hash[]
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2021-01-02 01:55:01 +01:00 |
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vhdl.awk
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |
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vhdl_netlist.c
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hash_hi() made faster by caching sch_path_hash[]
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2021-01-02 01:55:01 +01:00 |
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xinit.c
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saving to file made 4x faster, this implies less latency due to undo buffer savings on freaking big schematics.
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2021-01-06 03:01:14 +01:00 |
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xschem.h
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saving to file made 4x faster, this implies less latency due to undo buffer savings on freaking big schematics.
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2021-01-06 03:01:14 +01:00 |
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xschem.help
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removed obsolete --a3page command option
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2020-12-20 20:42:07 +01:00 |
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xschem.tcl
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more flexibility in constrained move operations (draw wires, lines, copy/move), pressing h/v again toggles constrained / unsonstrained move
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2021-01-05 01:24:45 +01:00 |
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xschemrc
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fix uncommented line (xschem start window) in xschemrc and link in doc main html page
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2021-01-05 03:53:55 +01:00 |
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