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hiertEDAx: don\t split on escaped white space. test schematic with weird instance/net names

This commit is contained in:
Stefan Frederik 2020-11-24 15:25:37 +01:00
parent a9a3538a71
commit d7b0c27775
5 changed files with 40 additions and 15 deletions
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25
src/flatten_tedax.awk
View File

@ -7,6 +7,10 @@ BEGIN{
hiersep="."
}
{
reparse()
}
/^begin netlist/{
cell = $4
if(first) {
@ -44,6 +48,7 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
hier++
for(i = start[cell]+1; i <= end[cell]-1; i++) {
$0 = netlist[i]
reparse()
# __subcircuit__ pcb_voltage_protection x0
# __map__ VOUT -> VOUTXX
# __map__ ... -> ...
@ -55,6 +60,7 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
out("#" spaces(hier * 2 - 1) $0)
for(i++; ;i++) {
$0 = netlist[i]
reparse()
if($1 != "__map__") break
dbg("expand: $4=" $4)
$4 = resolve_node($4, path, maplist)
@ -64,6 +70,7 @@ function expand(cell, instname, path, maplist, i, j, subpos, subcell, subi
}
expand(subcell, subinst, path subinst hiersep, submaplist)
$0 = netlist[i] # restore $0 after recursive call
reparse()
}
if($1 == "conn") {
dbg("conn: $2=" $2)
@ -102,7 +109,13 @@ function dbg(s)
function resolve_node(node, path, maplist, arr, n, retnode, i)
{
dbg("resolve_node: node=" node " maplist=" maplist)
gsub(/\\ /, SUBSEP "s", maplist)
gsub(/\\\t/, SUBSEP "t", maplist)
n = split(maplist, arr)
for(i = 1; i <= n; i++) {
gsub(SUBSEP "s", "\\ ", arr[i])
gsub(SUBSEP "t", "\\\t", arr[i])
}
if(node in global) retnode = node
else for(i = 1; i <= n; i += 2) {
if(node == arr[i]) {
@ -113,3 +126,15 @@ function resolve_node(node, path, maplist, arr, n, retnode, i)
if(retnode =="") retnode = path node
return retnode
}
# avoid considering escaped white spaces as field separators
function reparse( i)
{
gsub(/\\ /, SUBSEP "s")
gsub(/\\\t/, SUBSEP "t")
for(i = 1; i <= NF; i++) {
gsub(SUBSEP "s", "\\ ", $i)
gsub(SUBSEP "t", "\\\t", $i)
}
}

6
src/tedax.awk
View File

@ -159,8 +159,10 @@ $1 ~ /^(comptag|spicedev|spiceval|value)$/ {
# avoid considering escaped spaces as field separators
function reparse( i)
{
gsub(/\\ /, SUBSEP)
gsub(/\\ /, SUBSEP "s")
gsub(/\\\t/, SUBSEP "t")
for(i = 1; i <= NF; i++) {
gsub(SUBSEP, "\\ ", $i)
gsub(SUBSEP "s", "\\ ", $i)
gsub(SUBSEP "t", "\\\t", $i)
}
}

4
src/token.c
View File

@ -2716,7 +2716,7 @@ const char *translate(int inst, const char* s)
c=*s++;
if(c=='\\') {
escape=1;
c=*s++;
c=*s++; /* do not remove: breaks translation of format strings in netlists (escaping $) */
}
else escape=0;
space=SPACE(c);
@ -2992,7 +2992,6 @@ const char *translate2(struct Lcc *lcc, int level, char* s)
size = CADCHUNKALLOC;
my_realloc(661, &result, size);
result[0] = '\0';
while (1) {
c = *s++;
if (c == '\\') {
@ -3020,7 +3019,6 @@ const char *translate2(struct Lcc *lcc, int level, char* s)
} else {
my_strdup2(332, &value1, get_tok_value(lcc[level].prop_ptr, token + 1, 2));
}
value = "";
if(get_tok_size) {
value = value1;

2
xschem_library/pcb/hierarchical_tedax.sch
View File

@ -48,7 +48,7 @@ N 390 -500 450 -500 { lab=VSS_ANALOG}
C {title.sym} 160 -30 0 0 {name=l2 author="Stefan"}
C {lab_pin.sym} 70 -470 0 1 {name=p8 lab=VCC12}
C {conn_8x1.sym} 50 -450 0 0 {name=C2}
C {lab_pin.sym} 1130 -400 0 0 {name=p1 lab=VSSLOAD}
C {lab_pin.sym} 1130 -400 0 0 {name=p1 lab=VSS\\ LOAD}
C {lm358.sym} 710 -240 0 0 {name=U3:1
spiceprefix=X
VCC=VCC

18
xschem_library/pcb/voltage_protection.sch
View File

@ -9,7 +9,7 @@ E {}
B 2 170 -840 1010 -100 {dash=4}
T {@name} 1010 -870 0 1 0.4 0.4 {}
T {@symname} 170 -870 0 0 0.4 0.4 {}
N 920 -520 920 -390 {lab=VCC_FIVE}
N 920 -520 920 -390 {lab=VCC\\ FIVE}
N 750 -360 880 -360 {lab=G}
N 920 -300 1010 -300 {lab=VOUT}
N 920 -170 920 -150 {lab=VSS}
@ -18,7 +18,7 @@ N 480 -310 480 -220 {lab=Z}
N 480 -390 710 -390 {lab=B}
N 480 -160 480 -130 {lab=VSSA}
N 480 -430 480 -390 {lab=B}
N 750 -520 750 -420 {lab=VCC_FIVE}
N 750 -520 750 -420 {lab=VCC\\ FIVE}
N 750 -260 750 -230 {lab=#net1}
N 750 -170 750 -150 {lab=VSS}
N 480 -390 480 -370 {lab=B}
@ -28,12 +28,12 @@ N 400 -160 400 -130 {lab=VSSA}
N 400 -220 480 -220 {lab=Z}
N 700 -320 800 -320 {lab=G}
N 700 -260 800 -260 {lab=#net1}
N 480 -520 480 -490 { lab=VCC_FIVE}
N 480 -520 920 -520 { lab=VCC_FIVE}
N 920 -710 920 -520 { lab=VCC_FIVE}
N 480 -520 480 -490 { lab=VCC\\ FIVE}
N 480 -520 920 -520 { lab=VCC\\ FIVE}
N 920 -710 920 -520 { lab=VCC\\ FIVE}
N 170 -710 310 -710 { lab=VCC_UNREG}
N 170 -630 310 -630 { lab=VSSA}
N 820 -710 920 -710 { lab=VCC_FIVE}
N 820 -710 920 -710 { lab=VCC\\ FIVE}
N 230 -740 230 -710 { lab=VCC_UNREG}
C {conn_3x1.sym} 300 -360 0 0 {name=C1}
C {opin.sym} 1010 -300 0 0 {name=p0 lab=VOUT}
@ -52,11 +52,11 @@ device=BZX5V1
footprint=acy(300)
xxxspiceprefix="#D#"}
C {lab_pin.sym} 480 -130 0 0 {name=l13 lab=VSSA}
C {res.sym} 480 -460 0 0 {name=R4 m=1 value=4.7K footprint=1206 device=resistor}
C {res.sym} 480 -460 0 0 {name=Rdivider\\ upper m=1 value=4.7K footprint=1206 device=resistor}
C {res.sym} 750 -200 0 0 {name=R5 m=1 value=470 footprint=1206 device=resistor}
C {gnd.sym} 750 -150 0 0 {name=l16 lab=VSS}
C {lab_wire.sym} 510 -390 0 0 {name=l0 lab=B}
C {res.sym} 480 -340 0 0 {name=R2 m=1 value=510 footprint=1206 device=resistor}
C {res.sym} 480 -340 0 0 {name=Rdivider\\ lower m=1 value=510 footprint=1206 device=resistor}
C {pmos.sym} 900 -360 0 0 {name=M2
model=IRLML6402
device=IRLML6402
@ -81,6 +81,6 @@ C {lab_wire.sym} 480 -260 0 0 {name=l3 lab=Z}
C {reg.sch} -120 -520 0 0 {name=x2}
C {ipin.sym} 170 -710 0 0 {name=p3 lab=VCC_UNREG}
C {ipin.sym} 170 -630 0 0 {name=p1 lab=VSSA}
C {lab_wire.sym} 690 -520 0 0 {name=l4 lab=VCC_FIVE}
C {lab_wire.sym} 690 -520 0 0 {name=l4 lab=VCC\\ FIVE}
C {diode.sym} 230 -770 0 0 {name=D1 model=D1N914 area=1 device=D1N914 footprint=acy(300)}
C {vdd.sym} 230 -800 0 0 {name=l5 lab=VCC}