Stefan Frederik 9dd68436cf Handling of duplicated pins in spice netlists, added test_doublepin.sch in examples/		2022-02-15 12:28:23 +01:00
..
binto7seg	add -pg also in LDFLAGS if --profile is requested; add little more margin in ps page exports	2021-01-06 00:12:04 +01:00
devices	reverted xcb since text quality is slightly better	2022-01-18 03:37:54 +01:00
examples	Handling of duplicated pins in spice netlists, added test_doublepin.sch in examples/	2022-02-15 12:28:23 +01:00
gschem_import	some parameter checks in xschem commands, global var removal in simulation help window - No use for production yet	2021-11-16 22:28:10 +01:00
logic	preserve ordering in verilog/VHDL signal/wire/reg declarations for consistent netlist hashing/checking	2021-12-15 15:17:45 +01:00
ngspice	allow wave alias naming, fix off-by-one errors in plot_raw_custom_data() calls	2022-02-14 17:51:18 +01:00
pcb	tedax example	2022-01-11 14:44:19 +01:00
rom8k	allow wave alias naming, fix off-by-one errors in plot_raw_custom_data() calls	2022-02-14 17:51:18 +01:00
rulz-r8c33	"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols	2020-09-30 00:30:48 +02:00
symgen	removed unused files	2020-08-24 10:01:41 +02:00
viewdraw_import	add viewdraw_import example schematic/symbol dir for user evaluation and Viewdraw/DxDesigner import testing	2022-01-15 13:31:45 +01:00
xTAG	populating xschem git repo	2020-08-08 15:47:34 +02:00
xschem_simulator	added missing symbols	2021-12-19 01:32:19 +01:00
Makefile	added "xschem_simulator" sample example directory for trying logic propagation of probed nets	2020-12-26 19:26:33 +01:00