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xschem
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xschem/xschem_library/devices
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Stefan Frederik cc993bfe44 added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
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adc_bridge.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
ammeter.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
arch_declarations.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
architecture.sym replaced @ character with ? for spice netlist node multiplicity tags, so translate() will not try to expand them, do not print erc warnings for "non electrical" symbols (architecture, package, port_attributes, use, etc), print_spice_element() result string will be forwarded to translate() if enclosed within tcleval(...), so all @vars will be expanded. translate() in turn will forward to tcl_hook() if necessary. 2020-10-14 23:15:05 +02:00
asrc.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
assign.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
attributes.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
bsource.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
bus_connect.sym devices/ symbol fixes 2020-10-06 03:20:56 +02:00
bus_connect_nolab.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
capa-2.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
capa.sym better text positioning (net_name) on some devices/ symbols 2020-10-17 01:07:18 +02:00
cccs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
ccvs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
code.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
code_shown.sym svg_draw(): do not print unused layer stylesheets, error check when opening file for printing 2020-12-22 18:31:08 +01:00
conn_3x1.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
conn_4x1.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
conn_8x1.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
conn_10x2.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
conn_14x1.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
connect.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
connector.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
crystal-2.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
crystal.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
dac_bridge.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
delay.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
delay_line.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
diode.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
flash_cell.sym removed some redundant calls in prepare_netlist_structs(), no full instance spatial rehash if adding a component, set template name initials for components in devices/ that do not map directly to spice elements to lowercase letters. 2020-10-18 23:58:40 +02:00
generic_pin.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
gnd.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
ind.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
iopin.sym slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically. 2020-10-11 01:38:28 +02:00
ipin.sym slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically. 2020-10-11 01:38:28 +02:00
isource.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
isource_arith.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
isource_pwl.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
isource_table.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
jumper.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
k.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
lab_generic.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
lab_pin.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
lab_show.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
lab_wire.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
launcher.sym xschem setprop made way faster if "fast" argument is provided. Example "clear probes" launcher object in mos_power_ampli.sch. 2020-10-19 02:07:17 +02:00
led.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
netlist.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_at_end.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_not_shown.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_not_shown_at_end.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
netlist_options.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
ngspice_get_expr.sym example schematic updated and improvements 2021-01-01 04:24:57 +01:00
ngspice_get_value.sym example schematic updated and improvements 2021-01-01 04:24:57 +01:00
ngspice_probe.sym ngspice_probe type set from "probe" to "ngprobe" to avoid clashes 2021-01-02 19:44:01 +01:00
nmos-sub.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
nmos.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
nmos3.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
nmos4.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
noconn.sym optimize unselect_all() 2020-09-30 02:53:20 +02:00
npn.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
opin.sym slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically. 2020-10-11 01:38:28 +02:00
package.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
package_not_shown.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
param.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
param_agauss.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
parax_cap.sym devices/ symbol fixes 2020-10-06 03:20:56 +02:00
pmos-sub.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
pmos.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00
pmos3.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
pmos4.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
pmoshv4.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
pmosnat.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
pnp.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
port_attributes.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
res.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
res_ac.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
rgb_led.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
spice_probe.sym remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes 2020-12-17 18:26:46 +01:00
spice_probe_vdiff.sym remove "m=1" in xyce spice netlists as xyce does not handle m param. Translate spice_probe ".save" to xyce ".print tran", handle different hierarchical expansion of voltage/current nodes in xyce for hierarchical ammeter/spice_probe probes 2020-12-17 18:26:46 +01:00
sqwsource.sym sqwsource: do not use tcleval, leave the simple expressions parsing to the simulator 2020-10-26 02:58:29 +01:00
switch.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
switch_ngspice.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
switch_v_xyce.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
title-2.sym NumLock and CapsLock check for windows 2020-09-22 21:02:51 +02:00
title.sym LICENSE cosmetic editing 2020-10-10 11:49:12 +02:00
use.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
var_res.sym added in the menu the (undocumented) "propagate-highlight" function (propagate through conductive elements) 2021-01-02 20:33:34 +01:00
vccs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
vcr.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
vcvs.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
vdd.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
verilog_delay.sch verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)... 2020-10-10 23:21:23 +02:00
verilog_delay.sym populating xschem git repo 2020-08-08 15:47:34 +02:00
verilog_preprocessor.sym verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)... 2020-10-10 23:21:23 +02:00
verilog_timescale.sym more consistent get_tok_value() regarding escaping 2020-11-29 01:59:17 +01:00
vsource.sym better text positioning (net_name) on some devices/ symbols 2020-10-17 01:07:18 +02:00
vsource_arith.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
vsource_pwl.sym "@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols 2020-09-30 00:30:48 +02:00
zener.sym allow tEDAx (flattened) netlisting of hierarchical schematics; added pcb/hierarchical_tedax example 2020-11-24 02:54:45 +01:00