Stefan Schippers
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f8f1626c1b
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cleanup in print_spice_element(), print_verilog_primitive(), print_vhdl_primitive(), print_tedax_element(), parselabel allows ~ in node names (XSPICE inversion operator)
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2020-10-13 02:52:37 +02:00 |
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Stefan Schippers
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6f80fdbf76
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fix once again an issue when working in symlinked directories and giving a relative .sch file path on cmdline; clean up print_spice_element(). JL to check if tclgetvar("env(PWD)") works on windows (xinit.c:1435)
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2020-10-13 01:07:28 +02:00 |
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Stefan Schippers
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b006c82bad
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slight resize in pin text size for better look. top frame in insert text dialog does not extend vertically.
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2020-10-11 01:38:28 +02:00 |
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Stefan Schippers
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617d708009
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verilog_preprocessor and verilog_timescale now use verilog_format instead of format (which is for spice), corrected verilog_netlist.c; better backslash and quote (") escaping and unescaping when using attribute select combobox; for unquoting use "xschem get_tok tok 2" instead of "xschem get_tok tok 0" + regsub ....(remove backslashes)...
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2020-10-10 23:21:23 +02:00 |
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Stefan Schippers
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31eac64d7a
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LICENSE cosmetic editing
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2020-10-10 11:49:12 +02:00 |
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Stefan Schippers
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898a8adfb2
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some clarifications of steps to be taken to simulate example rom8k circuit
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2020-10-08 23:24:27 +02:00 |
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Stefan Schippers
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bbc5a58568
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added vsqsource, square wave source generator, with only "hi" and "freq" as parameters
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2020-10-07 18:04:03 +02:00 |
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Stefan Schippers
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d9488fa5ea
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small sample xschemrc fix
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2020-10-06 21:59:23 +02:00 |
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Stefan Schippers
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71f23a5242
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devices/ symbol fixes
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2020-10-06 03:20:56 +02:00 |
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Stefan Schippers
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11d664b4a8
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fix a memory leak, spatial hash table tuning, better clear find_inst_to_be_redrawn() nodetable
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2020-10-05 13:29:57 +02:00 |
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Stefan Schippers
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72363cf2d4
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better wire bbox calculation in find_inst_to_be_redrawn()
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2020-10-05 04:18:31 +02:00 |
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Stefan Schippers
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82051a33e5
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simplify / break down complex expressions for code readability
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2020-10-05 03:00:40 +02:00 |
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Stefan Schippers
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34a929f2bf
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fix rlc.sch sample circuit it was changed for debugging
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2020-10-03 12:51:31 +02:00 |
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Stefan Schippers
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72f0031611
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mos_power_ampli.sym and solar_panel.sch examples updated to display symbolnet names on pins
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2020-10-02 15:45:30 +02:00 |
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Stefan Schippers
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cf0db629c4
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make move operations display updated @#n:net_name attributes after move operation
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2020-10-01 02:58:05 +02:00 |
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Stefan Schippers
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3f482fd8a4
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optimize unselect_all()
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2020-09-30 02:53:20 +02:00 |
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Stefan Schippers
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0fe9c1223d
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doc updates
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2020-09-30 01:34:18 +02:00 |
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Stefan Schippers
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91e74fadcb
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"@#n:net_name" attribute (n = pin name or number) in symbols translates to net name attached to pin. "lab_show.sym" component that shows (does not assign) net name. "highlight=true" attribute can be given on instances in addition to symbols
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2020-09-30 00:30:48 +02:00 |
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Stefan Schippers
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f699d187e6
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save embedded components not only on first embeded instance but on all of them. This makes reloading easier and the overall thing much simpler. In LCC schematic allow get_sym_type() to read symbol data from folowing embedded tags "[...]" if any. Fix potential segfault in preview_window()
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2020-09-29 11:17:10 +02:00 |
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Stefan Schippers
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59d4608ac0
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completely eliminated match_symbol() (which in turn may call load_sym_def() ) calls from within load_sym_def(), even for aligning LCC schematic pin ordering to symbol. A dedicated "align_sch_pins_with_sym()" together with "get_sym_type()" does the job in O(N) instead of using a sort routine.
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2020-09-27 12:41:36 +02:00 |
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Stefan Schippers
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b5d21e54f1
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removed debug messages
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2020-09-26 01:29:28 +02:00 |
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Stefan Schippers
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c627f21057
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optimize previous fix, avod skipping lines after embedded symbol (embed_fd)
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2020-09-24 17:46:58 +02:00 |
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Stefan Schippers
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b7d724dcab
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apply visible layers (View->Symbol visible layers) to any object (lines. arcs, text etc),better bounding box calculation for slant text
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2020-09-23 22:13:39 +02:00 |
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Stefan Schippers
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5e98241df1
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NumLock and CapsLock check for windows
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2020-09-22 21:02:51 +02:00 |
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Stefan Schippers
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82451fd50e
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"xschem hilight_netname" command to hilight a specific net name, "xschem search exact ..." finds specific instances of vector instances, "probe_net" procedure descends into the right bussed instance and hilights the correct net bit, added "xschem display_hilights" to return all hilighted nets in the hierarchy, added "gaw_cmd" procedure to send socket commands to gaw (like "gaw_cmd reload_all") (recently added command to gaw ttg)
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2020-09-22 13:35:55 +02:00 |
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Stefan Schippers
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1a2500291d
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dash attribute for arcs
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2020-09-02 23:59:58 +02:00 |
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Stefan Schippers
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a44302a7fd
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better join/end style for dashed objects, some dashed objects in example schematics/symbols
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2020-09-02 19:21:51 +02:00 |
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Stefan Schippers
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3107c5b12a
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added "dash=n" (n=integer) attribute for lines, polygons, rectangles to set dashed line style. n is the dash length in pixels.
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2020-09-02 18:28:20 +02:00 |
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Stefan Schippers
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e6fe276eba
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undo test-changes in example schematics
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2020-09-02 13:16:54 +02:00 |
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Stefan Schippers
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9f82cf47aa
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verilog_ignore, spice_ignore, vhdl_ignore attributes on schematic pins are propagated to symbol pin attributes (if using make symbol from schematic, otherwise propagate by hand). These pins are not netlisted in the respective netlist format
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2020-09-02 12:30:52 +02:00 |
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Stefan Schippers
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b2289683ac
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doc updates for text hcenter and vcenter attrs
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2020-08-25 02:10:15 +02:00 |
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Stefan Schippers
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ec29c2677a
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enable "preserve unchanged props" checkbutton in text edit prop dialog box
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2020-08-24 16:21:50 +02:00 |
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Stefan Schippers
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bd982c00ce
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removed unused files
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2020-08-24 10:01:41 +02:00 |
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Stefan Schippers
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b842e020bc
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snap and grid entries will not annoyingly receive keyboard focus with TAB key
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2020-08-19 15:08:35 +02:00 |
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Stefan Schippers
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7f6b3d999f
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fixed symbol text
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2020-08-18 10:32:33 +02:00 |
schippes
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9570439e16
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made edit_symbol_property and tcl edit_prop procedure much simpler when user clicks another instance while edit_prop dialog still open
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2020-08-16 03:34:45 +02:00 |
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schippes
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58a43ccc4d
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code cleanups, preparing for editprop combobox token selector
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2020-08-15 10:48:26 +02:00 |
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schippes
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ff9e2e7872
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when copying a symbol with edit_property dialog ("q" key) and enabling "Copy cell" if a relative path name is supplied for new symbol it will inherit the same path prefix as the original symbol.
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2020-08-13 12:56:20 +02:00 |
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schippes
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ea4513f9c5
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changed tcl procs abs_sym_path and rel_sym_path, now the real symbol filename is obtained by prepending one of the XSCHEM_LIBRARY_PATH paths until the symbol is found. This allows more than one directory levels in symbol references.
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2020-08-13 02:19:08 +02:00 |
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schippes
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c5f412bdb7
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symbol attribute @symname will display symbol name without extension as it used to be in earlier versions. @symname_ext will print full rootname of symbol. Some doc updates on symbol attributes
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2020-08-12 11:31:42 +02:00 |
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schippes
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8dac4753f7
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Verilog and vhdl netlisters: print as instance parameters all params listed in instance properties, excluding "name" and all params not listed in template
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2020-08-10 14:15:36 +02:00 |
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Stefan SChippers
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5e8df730a0
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populating xschem git repo
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2020-08-08 15:47:34 +02:00 |