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undo test-changes in example schematics

This commit is contained in:
Stefan Schippers 2020-09-02 13:16:54 +02:00
parent 9f82cf47aa
commit e6fe276eba
2 changed files with 2 additions and 2 deletions
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2
xschem_library/examples/mos_power_ampli.sch
View File

@ -258,5 +258,5 @@ C {spice_probe.sym} 340 -820 0 1 {name=p51 analysis=tran voltage=49.03}
C {spice_probe.sym} 120 -210 0 1 {name=p52 analysis=tran voltage=-42.58}
C {spice_probe.sym} 130 -70 0 1 {name=p53 analysis=tran voltage=-50}
C {opin.sym} 600 -130 0 0 {name=p5 lab=OUT}
C {ipin.sym} 530 -180 0 0 {name=p1 lab=MINUS spice_ignore=true verilog_ignore=true vhdl_ignore=true}
C {ipin.sym} 530 -180 0 0 {name=p1 lab=MINUS}
C {ipin.sym} 530 -140 0 0 {name=p4 lab=VSS}

2
xschem_library/examples/mos_power_ampli.sym
View File

@ -10,7 +10,7 @@ L 4 -130 -50 130 -50 {}
L 4 -130 50 130 50 {}
L 4 -130 -50 -130 50 {}
L 4 130 -50 130 50 {}
B 5 -152.5 -42.5 -147.5 -37.5 {name=MINUS dir=in name=p1 spice_ignore=true verilog_ignore=true vhdl_ignore=true}
B 5 -152.5 -42.5 -147.5 -37.5 {name=MINUS dir=in name=p1 }
L 4 -150 -40 -130 -40 {}
T {MINUS} -125 -44 0 0 0.2 0.2 {}
B 5 -152.5 -22.5 -147.5 -17.5 {name=PLUS dir=in name=p0 }