xschem/xschem_library/examples/cmos_example.sch

v {xschem version=3.4.5 file_version=1.2
*
* This file is part of XSCHEM,
* a schematic capture and Spice/Vhdl/Verilog netlisting tool for circuit
* simulation.
* Copyright (C) 1998-2023 Stefan Frederik Schippers
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
}
G {}
K {}
V {}
S {}
E {}
B 2 1690 -960 2250 -630 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_dc.raw)
sim_type=dc
y1=-160
y2=-0.78
divy=4
subdivy=1
x1=2.3
x2=2.7
divx=6
subdivx=1
node="\\"GAIN @ 2uA;diffout deriv() % 0\\"
\\"GAIN @ 10uA;diffout deriv() % 1\\"
\\"GAIN @ 100uA;diffout deriv() % 2\\""
color="10 12 6"
dataset=-1}
B 2 190 -760 327 -700 {flags=image
alpha=0.6
InvertOnExport=true
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B 2 20 -757.5 158 -695 {flags=image
alpha=0.6
InvertOnExport=true
image=/home/schippes/x/xyce.png
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B 2 1690 -620 2250 -300 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_dc.raw)
sim_type=dc
y1=0.875402
y2=5.6754
divy=4
subdivy=1
x1=2.3
x2=2.7
divx=6
subdivx=1
node="diffout@2uA;v(diffout)%0
diffout@10uA;v(diffout)%1
diffout@100uA;v(diffout)%2"
color="10 12 6"
dataset=-1
}
B 2 1050 -470 1680 -190 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_tran.raw)
sim_type=tran
y1=0.578703
y2=5.5787
divy=5
subdivy=1
x1=0
x2=5e-06
divx=6
subdivx=1



dataset=-1
color="10 12 6"
node="\\"diffout 2uA; diffout%0\\"
\\"diffout 10uA; diffout%1\\"
\\"diffout 100uA; diffout%2\\""
hilight_wave=-1
xlabmag=1.4}
B 2 1050 -740 1680 -530 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_ac.raw)
sim_type=ac
y1=-53
y2=43

subdivy=1
x1=0.295931
x2=9.29594
divx=6
subdivx=8



dataset=-1
color="10 12 6"
node="\\"gain 2uA; diffout db20()%0\\"
\\"gain 10uA; diffout db20()%1\\"
\\"gain 10uA; diffout db20()%2\\""
hilight_wave=-1
logx=1
xlabmag=1.4
divy=5
ylabmag=1.2}
B 2 1050 -960 1680 -750 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_ac.raw)
sim_type=ac
y1=37
y2=180
divy=4
subdivy=1
x1=0.295931
x2=9.29594
divx=6
subdivx=8



dataset=-1
color="10 12 6"
node="\\"phase 2uA; ph(diffout)%0\\"
\\"phase 10uA; ph(diffout)%1\\"
\\"phase 100uA; ph(diffout)%2\\""
hilight_wave=-1
logx=1
xlabmag=1.4}
B 2 1690 -290 2250 -20 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_dc.raw)
sim_type=dc
y1=2.3
y2=2.7
divy=4
subdivy=1
x1=2.3
x2=2.7
divx=6
subdivx=1
node="minus;minus%0
plus;plus%0"
color="7 8"
dataset=-1
}
B 2 1050 -180 1680 -60 {flags=graph,unlocked
rawfile=tcleval($netlist_dir/cmos_example_ngspice_tran.raw)
sim_type=tran
y1=2.4
y2=2.6
divy=2
subdivy=1
x1=0
x2=5e-06
divx=6
subdivx=1



dataset=-1
color="7 8"
node="minus;minus%0
plus;plus%0"
hilight_wave=-1
ylabmag=1.4
xlabmag=1.4}
T {CMOS DIFFERENTIAL AMPLIFIER
EXAMPLE. DC simulation} 30 -680 0 0 0.4 0.4 {}
T {tcleval([xschem raw info])} 20 -960 0 0 0.5 0.5 {floater=true layer=16}
T {AC Analysis} 1060 -1010 0 0 0.6 0.6 { layer=6}
T {Transient Analysis} 1060 -510 0 0 0.6 0.6 { layer=6}
T {DC Analysis} 1690 -1000 0 0 0.6 0.6 { layer=6}
T {Loaded Raw files:} 20 -1010 0 0 0.6 0.6 {}
N 30 -310 30 -280 {
lab=VCC}
N 30 -310 60 -310 {
lab=VCC}
N 260 -240 260 -190 {
lab=GN}
N 260 -190 300 -190 {
lab=GN}
N 300 -190 300 -160 {
lab=GN}
N 300 -160 530 -160 {
lab=GN}
N 500 -290 520 -290 {
lab=0}
N 670 -290 690 -290 {
lab=0}
N 500 -260 690 -260 {
lab=S}
N 440 -290 460 -290 {
lab=PLUS}
N 730 -290 750 -290 {
lab=MINUS}
N 690 -490 740 -490 {
lab=VCC}
N 450 -490 500 -490 {
lab=VCC}
N 540 -490 650 -490 {
lab=G}
N 540 -490 540 -460 {
lab=G}
N 500 -460 540 -460 {
lab=G}
N 690 -560 690 -520 {
lab=VCC}
N 500 -560 690 -560 {
lab=VCC}
N 500 -560 500 -520 {
lab=VCC}
N 570 -580 570 -560 {
lab=VCC}
N 690 -420 830 -420 {
lab=DIFFOUT}
N 30 -440 30 -410 {
lab=MINUS}
N 30 -440 60 -440 {
lab=MINUS}
N 30 -590 30 -560 {
lab=PLUS}
N 30 -590 60 -590 {
lab=PLUS}
N 570 -130 570 -100 {
lab=0}
N 570 -130 590 -130 {
lab=0}
N 590 -160 590 -130 {
lab=0}
N 570 -160 590 -160 {
lab=0}
N 260 -130 260 -100 {
lab=0}
N 240 -130 260 -130 {
lab=0}
N 240 -160 240 -130 {
lab=0}
N 240 -160 260 -160 {
lab=0}
N 690 -460 690 -400 {
lab=DIFFOUT}
N 570 -260 570 -250 {
lab=S}
N 500 -340 500 -320 {
lab=#net1}
N 570 -250 570 -190 {
lab=S}
N 690 -340 690 -320 {
lab=#net2}
N 500 -460 500 -400 {
lab=G}
C {lab_pin.sym} 750 -360 0 0 {name=p20 lab=0  net_name=true}
C {lab_pin.sym} 30 -220 0 0 {name=p17 lab=0  net_name=true}
C {title.sym} 160 -30 0 0 {name=l1 author="Stefan Schippers"  net_name=true}
C {nmos4.sym} 550 -160 0 0 {name=m1 model=cmosn w=5u l=2u m=1  net_name=true}
C {pmos4.sym} 670 -490 0 0 {name=m2 model=cmosp w=5u l=2u m=1  net_name=true}
C {vsource.sym} 30 -250 0 0 {name=VVCC value='VCC'  net_name=true
}
C {lab_pin.sym} 570 -100 0 0 {name=p1 lab=0  net_name=true}
C {lab_pin.sym} 60 -310 0 1 {name=p2 lab=VCC  net_name=true}
C {nmos4.sym} 280 -160 0 1 {name=m3 model=cmosn w=5u l=2u m=1  net_name=true}
C {lab_pin.sym} 260 -100 0 0 {name=p3 lab=0  net_name=true}
C {isource.sym} 260 -270 0 0 {name=IBIAS value='IB'  net_name=true
}
C {lab_pin.sym} 260 -300 0 0 {name=p4 lab=0  net_name=true}
C {nmos4.sym} 480 -290 0 0 {name=m4 model=cmosn w=10u l=1u m=1  net_name=true}
C {lab_pin.sym} 520 -290 0 1 {name=p5 lab=0  net_name=true}
C {nmos4.sym} 710 -290 0 1 {name=m5 model=cmosn w=10u l=1u m=1  net_name=true}
C {lab_pin.sym} 670 -290 0 0 {name=p0 lab=0  net_name=true}
C {lab_pin.sym} 740 -490 0 1 {name=p6 lab=VCC  net_name=true}
C {pmos4.sym} 520 -490 0 1 {name=m6 model=cmosp w=5u l=2u m=1  net_name=true}
C {lab_pin.sym} 450 -490 0 0 {name=p7 lab=VCC  net_name=true}
C {lab_pin.sym} 570 -580 0 0 {name=p8 lab=VCC  net_name=true}
C {lab_pin.sym} 440 -290 0 0 {name=p9 lab=PLUS  net_name=true}
C {lab_pin.sym} 750 -290 0 1 {name=p10 lab=MINUS  net_name=true}
C {lab_pin.sym} 830 -420 0 1 {name=p11 lab=DIFFOUT  net_name=true}
C {lab_pin.sym} 260 -220 0 0 {name=p13 lab=GN  net_name=true}
C {lab_pin.sym} 30 -350 0 0 {name=p14 lab=0  net_name=true}
C {vsource.sym} 30 -380 0 0 {name=VPLUS
value="2.5 pulse 2.4 2.6 10n 1n 1n 0.999u 2u ac 1 0" 
net_name=true
}
C {lab_pin.sym} 60 -440 0 1 {name=p15 lab=MINUS  net_name=true}
C {lab_pin.sym} 30 -500 0 0 {name=p16 lab=0  net_name=true}
C {vsource.sym} 30 -530 0 0 {name=V1 value=2.5  net_name=true}
C {lab_pin.sym} 60 -590 0 1 {name=p18 lab=PLUS  net_name=true}
C {capa.sym} 750 -390 0 0 {name=CL
m=1
value=0.2p
footprint=1206
device="ceramic capacitor"  net_name=true}
C {lab_pin.sym} 500 -430 0 0 {name=p12 lab=G  net_name=true}
C {launcher.sym} 700 -60 0 0 {name=h1
descr=Backannotate
tclcommand="xschem annotate_op $\{netlist_dir\}/cmos_example_ngspice_op.raw"
}
C {launcher.sym} 700 -110 0 0 {name=h2
descr="View raw file"
tclcommand="textwindow $netlist_dir/cmos_example_ngspice.raw"}
C {ngspice_get_value.sym} 620 -160 0 0 {name=r5 node=i(@$\{path\}m1[id])
descr="I="}
C {launcher.sym} 475 -695 0 0 {name=h3 
descr="Load NGSPICE waveforms (ctrl-left-click)" 
tclcommand="
xschem raw_read $netlist_dir/cmos_example_ngspice.raw dc
"
}
C {launcher.sym} 1310 -30 0 0 {name=h4
descr="Graph Manual page"
url="https://xschem.sourceforge.io/stefan/xschem_man/graphs.html"}
C {ammeter.sym} 690 -370 0 1 {name=Vmeasr}
C {simulator_commands.sym} 920 -360 0 0 {name=COMMANDS
simulator=ngspice
only_toplevel=true 
value=".temp 30
.param IB=2u
.param VCC = 5
** models are generally not free: you must download
** SPICE models for active devices and put them into the below 
** referenced file in netlist/simulation directory.
** http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s00/ASSIGNMENTS/TSMC035-n96g-params.txt
.include \\"models_cmos_example.txt\\"
.option savecurrents
.save all @m4[gm] @m5[gm] @m1[gm]
.control
  save all
  op
  write cmos_example_ngspice_op.raw
  dc vplus 2.3 2.7 0.001
  write cmos_example_ngspice_dc.raw
  tran 0.5n 5u
  write cmos_example_ngspice_tran.raw
  ac dec 10 1 1G
  remzerovec
  write cmos_example_ngspice_ac.raw

  set appendwrite
  alterparam IB=10u
  reset
  save all
  dc vplus 2.4 2.6 0.001
  write cmos_example_ngspice_dc.raw
  tran 0.5n 5u
  write cmos_example_ngspice_tran.raw
  ac dec 10 1 1G
  remzerovec
  write cmos_example_ngspice_ac.raw

  alterparam IB=100u
  reset
  save all
  dc vplus 2.3 2.7 0.001
  write cmos_example_ngspice_dc.raw
  tran 0.5n 5u
  write cmos_example_ngspice_tran.raw
  ac dec 10 1 1G
  remzerovec
  write cmos_example_ngspice_ac.raw
.endc

"}
C {launcher.sym} 475 -655 0 0 {name=h6 
descr="Load XYCE waveforms (ctrl-left-click)" 
tclcommand="
xschem raw_read $netlist_dir/cmos_example_xyce.raw
"
}
C {simulator_commands.sym} 920 -180 0 0 {name=COMMANDS1
simulator=xyce
only_toplevel=true 
value="* .temp 30
.param IB=100u
.param VCC = 5
** models are generally not free: you must download
** SPICE models for active devices and put them into the below 
** referenced file in netlist/simulation directory.
** http://bwrcs.eecs.berkeley.edu/Classes/icdesign/ee241_s00/ASSIGNMENTS/TSMC035-n96g-params.txt
.include \\"models_cmos_example.txt\\"
.print dc format=raw file=cmos_example_xyce.raw
+ v(*) i(*)
.op
.dc vplus 2.3 2.7 0.001

"}
C {ngspice_get_value.sym} 520 -310 0 0 {name=r6 node=i(@$\{path\}m4[id])
descr="I="}
C {ngspice_get_value.sym} 670 -310 0 1 {name=r7 node=i(@$\{path\}m5[id])
descr="I="}
C {ngspice_get_expr.sym} 160 -150 0 0 {name=r8 node="[to_eng [expr \{[ngspice::get_voltage gn] * [ngspice::get_current \{m3[id]\}]\}]]"
descr="Power="
}
C {ammeter.sym} 500 -370 0 1 {name=Vmeasl}
C {lab_pin.sym} 570 -230 0 0 {name=p19 lab=S  net_name=true}
C {launcher.sym} 475 -735 0 0 {name=h5 
descr="Switch rawfile" 
tclcommand="
xschem raw switch; xschem redraw"

}