Version bump

git-svn-id: file://localhost/svn/verilator/trunk/verilator@915 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,9 +3,64 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.650 4/20/2007
+
+**   Add --compiler msvc option.  This is now required when Verilated code
+     is to be run through MSVC++.  This also enables fixing MSVC++ error
+     C1061, blocks nested too deeply.  [Ralf Karge]
+
+**   Add --lint-only option, to lint without creating other output.
+
+***  Add /*verilator lint_save*/ and /*verilator lint_restore*/ to allow
+     friendly control over re-enabling lint messages.  [Gerald Williams]
+
+***  Support SystemVerilog .name and .* interconnect.
+
+***  Support while and do-while loops.
+
+***  Use $(LINK) instead of $(CXX) for Makefile link rules.  [Gerald Williams]
+
+***  Add USER_CPPFLAGS and USER_LDFLAGS to Makefiles.  [Gerald Williams]
+
+**** Fix compile errors under Windows MINGW compiler.  [Gerald Williams]
+
+**** Fix dotted bit reference to local memory.  [Eugene Weber]
+
+**** Fix 3.640 `verilog forcing IEEE 1364-1995 only.  [David Hewson]
+
+* Verilator 3.640 3/12/2007
+
+***  Support Verilog 2005 `begin_keywords and `end_keywords.
+
+***  Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005.
+
+***  Add /*verilator public_flat*/.  [Eugene Weber]
+
+**** Try all +libext's in the exact order given.  [Michael Shinkarovsky]
+
+**** Fix elimination of public signals assigned to constants.  [Eugene Weber]
+
+**** Fix internal error when public for loop has empty body.  [David Addison]
+
+**** Fix "Loops detected" assertion when model exceeds 4GB.  [David Hewson]
+
+**** Fix display %m names inside named blocks.
+
+* Verilator 3.633 2/7/2007
+
+***  Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto]
+
+***  With VL_DEBUG, show wires causing convergence errors. [Mike Shinkarovsky]
+
+**** Fix isolate_assignments when many signals per always. [Mike Shinkarovsky]
+
+**** Fix isolate_assignments across task/func temporaries. [Mike Shinkarovsky]
+
+**** Fix $display's with array select followed by wide AND.  [David Hewson]
+
 * Verilator 3.632 1/17/2007
 
-***  Add /*verilator isolate_asignments*/ attribute.  [Mike Shinkarovsky]
+***  Add /*verilator isolate_assignments*/ attribute.  [Mike Shinkarovsky]
 
 * Verilator 3.631 1/2/2007
 
@@ -83,7 +138,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Removed coverage request variable; see Coverage limitations in docs.
 
-**** Fix DOS carrage returns in multiline defines.  [Ralf Karge]
+**** Fix DOS carriage returns in multiline defines.  [Ralf Karge]
 
 **** Fix printf format warnings on 64-bit linux.
 
@@ -95,7 +150,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 ***  Added --inhibit-sim flag for environments using old __Vm_inhibitSim.
 
-***  Added `systemc_dtor for destructor extentions.  [Allan Cochrane]
+***  Added `systemc_dtor for destructor extensions.  [Allan Cochrane]
 
 ***  Added -MP to make phony dependencies, ala GCC's.
 
@@ -130,7 +185,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix extraneous UNSIGNED warning when comparing genvars.  [David Hewson]
 
-**** Fix extra whitespace in $display %c.  [by David Addison]
+**** Fix extra white space in $display %c.  [by David Addison]
 
 **** vl_finish and vl_fatal now print via VL_PRINTF rather then cerr/cout.
 
@@ -233,7 +288,7 @@ indicates the contributor was also the author of the fix; Thanks!
 
 **** Fix functions where regs are declared before inputs.  [Danny Ding]
 
-**** Fix bad deep expressions with bitselects and rotate.  [Prabhat Gupta]
+**** Fix bad deep expressions with bit-selects and rotate.  [Prabhat Gupta]
 
 * Verilator 3.500 10/30/2005 Stable
 

TODO

@@ -47,6 +47,10 @@ Testing:
 	Better graph viewer with search and zoom
 	Port and test against opencores.org code
 
+Usability:
+	Better reporting of unopt problems, including what lines of code
+	Report more errors (all of them?) before exiting [Eugene Weber]	
+
 Performance:
 	Constant propagation
 		Extra cleaning AND:  1 & ((VARREF >> 1) | ((&VARREF >> 1) & VARREF))

bin/verilator

@@ -104,10 +104,11 @@ if ($Opt_Sp) {
 }
 if ($Opt_Sp eq 'sp' || $Opt_Trace) {
     if (!defined $ENV{SYSTEMPERL}) {
-	my $try = "$ENV{W}/hw/utils/perltools/SystemC/src";
+	my $try = "$ENV{W}/hw/utils/perltools/SystemC";
 	$ENV{SYSTEMPERL} = $try if -d $try;
     }
     (defined $ENV{SYSTEMPERL}) or die "%Error: verilator: Need \$SYSTEMPERL in environment for --sp or --trace\nProbably System-Perl isn't installed, see http://www.veripool.com/systemperl.html\n";
+    (-d "$ENV{SYSTEMPERL}/src") or die "%Error: verilator: \$SYSTEMPERL environment var doesn't seem to point to System-Perl kit\n";
 }
 
 # Determine runtime flags
@@ -190,6 +191,7 @@ Verilator - Convert Verilog code to C++/SystemC
     verilator --cc [options] [top_level.v] [opt_c_files.cpp/c/cc]
     verilator --sc [options] [top_level.v] [opt_c_files.cpp/c/cc]
     verilator --sp [options] [top_level.v] [opt_c_files.cpp/c/cc]
+    verilator --lint-only ...
 
 =head1 DESCRIPTION
 
@@ -244,6 +246,27 @@ output files.
 
 Specifies C++ without SystemC output mode; see also --sc and --sp.
 
+=item --compiler I<compiler-name>
+
+Enables tunings and work-arounds for the specified C++ compiler.
+
+=over 4
+
+=item gcc
+
+Tune for Gnu C++, although generated code should work on almost any
+compliant C++ compiler.  Currently the default.
+
+=item msvc
+
+Tune for Microsoft Visual C++.  This may reduce execution speed as it
+enables several workarounds to avoid silly hardcoded limits in MSVC++.
+This includes breaking deeply nested parenthesized expressions into
+sub-expressions to avoid error C1009, and breaking deep blocks into
+functions to avoid error C1061.
+
+=back
+
 =item --coverage
 
 Enables all forms of coverage, alias for --coverage-line, --coverage-user
@@ -324,9 +347,13 @@ change the SystemC modules instantiated.
 Tune the inlining of modules.  The default value of 2000 specifies that up
 to 2000 new operations may be added to the model by inlining, if more then
 this number of operations would result, the module is not inlined.  Larger
-values, or -1 to inline everything, will lead to longer compile times, but
-potentially faster runtimes.  This setting is ignored for very small
-modules; they will always be inlined, if allowed.
+values, or a value <= 1 will inline everything, will lead to longer compile
+times, but potentially faster runtimes.  This setting is ignored for very
+small modules; they will always be inlined, if allowed.
+
+=item --lint-only
+
+Check the files for lint violations only, do not create any other output.
 
 =item --MMD
 
@@ -422,8 +449,8 @@ enable functional coverage.
 
 =item --public
 
-This is only for debug, and may result in mis-simulation of generated
-clocks.
+This is only for historical debug use.  Using it may result in
+mis-simulation of generated clocks.
 
 Declares all signals and modules public.  This will turn off signal
 optimizations as if all signals had a /*verilator public*/ comments and
@@ -449,6 +476,13 @@ Adds waveform tracing code to the model.  Having tracing compiled in may
 result in some small performance losses, even when waveforms are not turned
 on during model execution.
 
+=item --trace-depth I<levels>
+
+Specify the number of levels deep to enable tracing, for example
+--trace-level 1 to only see the top level's signals.  Defaults to the
+entire model.  Using a small number will decrease visibility, but greatly
+improve runtime and trace file size.
+
 =item --underline-zero
 
 Rarely needed.  Signals starting with a underline should be initialized to
@@ -543,6 +577,7 @@ We'll compile this example into C++.
       int main(int argc, char **argv, char **env) {
           Vour* top = new Vour;
           while (!Verilated::gotFinish()) { top->eval(); }
+          exit(0);	
       }
     EOF
 
@@ -596,13 +631,13 @@ This is an example similar to the above, but using SystemPerl.
 
     cat <<EOF >sc_main.cpp
       #include "Vour.h"
-      #include "systemperl.h"
       int sc_main(int argc, char **argv) {
           sc_clock clk ("clk",10, 0.5, 3, true);
           Vour* top;
-          SP_CELL (top, Vour);
-          SP_PIN  (top, clk, clk);
+          top = new Vour("top");   // SP_CELL (top, Vour);
+          top->clk(clk);           // SP_PIN  (top, clk, clk);
           while (!Verilated::gotFinish()) { sc_start(1); }
+          exit(0);	
       }
     EOF
 
@@ -677,11 +712,13 @@ fast path, mostly code that is executed every cycle.  OPT_SLOW specifies
 optimizations for slow-path files (plus tracing), which execute only
 rarely, yet take a long time to compile with optimization on.  OPT
 specifies overall optimization and affects all compiles, including those
-OPT_FAST and OPT_SLOW affect.  For best results, use OPT="-O2".  Nearly the
-same results can be had with much better compile times with OPT_FAST="-O1
--fstrict-aliasing".  Unfortunately, using the optimizer with SystemC files
-can result in compiles taking several minutes.  (The SystemC libraries have
-many little inlined functions that drive the compiler nuts.)
+OPT_FAST and OPT_SLOW affect.  For best results, use OPT="-O2", and link
+with "-static".  Nearly the same results can be had with much better
+compile times with OPT_FAST="-O1 -fstrict-aliasing".
+
+Unfortunately, using the optimizer with SystemC files can result in
+compiles taking several minutes.  (The SystemC libraries have many little
+inlined functions that drive the compiler nuts.)
 
 For best results, use GCC 3.3 or newer.  GCC 3.2 and earlier have
 optimization bugs around pointer aliasing detection, which can result in 2x
@@ -702,7 +739,10 @@ how Verilator compares, and may be able to suggest additional improvements.
 
 =head1 FILES
 
-Verilator creates the following files:
+All output files are placed in the output directory name specified with the
+-Mdir option, or "obj_dir" if not specified.
+
+Verilator creates the following files in the output directory:
 
     {prefix}.mk				// Make include file for compiling
     {prefix}_classes.mk			// Make include file with class names
@@ -714,7 +754,7 @@ For -cc and -sc mode, it also creates:
     {prefix}{each_verilog_module}.cpp	// Lower level internal C++ files
     {prefix}{each_verilog_module}.h	// Lower level internal header files
 
-For -sp mode, it also creates:
+For -sp mode, instead of .cpp and .h it creates:
 
     {prefix}.sp				// Top level SystemC file
     {prefix}{each_verilog_module}.sp	// Lower level internal SC files
@@ -736,7 +776,8 @@ It also creates internal files that can be mostly ignored:
     {prefix}{misc}.dot			// Debugging graph files (--debug)
     {prefix}{misc}.tree			// Debugging files (--debug)
 
-After running Make, the compiler will produce the following:
+After running Make, the C++ compiler should produce the following:
+
     {prefix}				// Final executable (w/--exe argument)
     {prefix}__ALL.a			// Library of all Verilated objects
     {prefix}{misc}.o			// Intermediate objects
@@ -883,30 +924,46 @@ The target system may also require edits to the Makefiles, the simple
 Makefiles produced by Verilator presume the target system is the same type
 as the build system.
 
-=head1 VERILOG 2001 SUPPORT
+=head1 VERILOG 2001 (IEEE 1364-2001) SUPPORT
 
-Verilator supports the more common Verilog 2001 language features.  This
+Verilator supports almost all Verilog 2001 language features.  This
 includes signed numbers, "always @*", comma separated sensitivity lists,
 generate statements, multidimensional arrays, localparam, and C-style
 declarations inside port lists.
 
-=head1 SYSTEMVERILOG 3.1 SUPPORT
+=head1 VERILOG 2005 (IEEE 1364-2005) SUPPORT
 
-Verilator currently has very minimal support for SystemVerilog.
+Verilator supports the `begin_keywords and `end_keywords compiler
+directives.
 
-Verilator implement the full SystemVerilog 3.1 preprocessor subset,
-including function call-like preprocessor defines.  Verilator also
-implements $bits, $countones, $isunknown, $onehot, and $onehot0,
-always_comb, always_ff, always_latch, and final.
+Verilator partially supports the uwire keyword.
+
+=head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
+
+Verilator currently has very minimal support for SystemVerilog. As
+SystemVerilog features enter common usage they will be added.  Contact the
+author if a feature you need is missing.
+
+Verilator implements the full SystemVerilog 1800-2005 preprocessor subset,
+including function call-like preprocessor defines.
+
+Verilator supports $bits, $countones, $error, $fatal, $info, $isunknown,
+$onehot, $onehot0, $warning, always_comb, always_ff, always_latch,
+do-while, and final.  It also supports .name and .* interconnection.
+
+Verilator partially supports assert.
 
 =head1 SUGAR/PSL SUPPORT
 
-With the --assert switch, Verilator is just beginning to support the
-Property Specification Language (PSL), specifically the simple subset
-without time-branching primitives.  Verilator currently only converts PSL
+Most future work is being directed towards improving SystemVerilog
+assertions instead of PSL.  If you are using these PSL features, please
+contact the author as they may be depreciated in future versions.
+
+With the --assert switch, Verilator enables support of the Property
+Specification Language (PSL), specifically the simple PSL subset without
+time-branching primitives.  Verilator currently only converts PSL
 assertions to simple "if (...) error" statements, and coverage statements
-to increment the line counters described in the coverage section.  If you
-need additional features please contact the author.
+to increment the line counters described in the coverage section.
 
 Verilator implements these keywords: assert, assume (same as assert),
 default (for clocking), countones, cover, isunknown, onehot, onehot0,
@@ -915,18 +972,16 @@ report, true.
 Verilator implements these operators: -> (logical if).
 
 Verilator does not support SEREs yet.  All assertion and coverage
-statements must be simple expressions that complete in one cycle.
-(Arguably SEREs are the whole point of PSL, but one must start somewhere.)
-
-PSL vmode/vprop/vunits are not supported.  PSL statements must be in the
-module they reference, at the module level where you would put an
+statements must be simple expressions that complete in one cycle.  PSL
+vmode/vprop/vunits are not supported.  PSL statements must be in the module
+they reference, at the module level where you would put an
 initial... statement.
 
 Verilator only supports (posedge CLK) or (negedge CLK), where CLK is the
 name of a one bit signal.  You may not use arbitrary expressions as
 assertion clocks.
 
-=head1 SYNTHESIS DIRECTIVE ASSERTIONS
+=head1 SYNTHESIS DIRECTIVE ASSERTION SUPPORT
 
 With the --assert switch, Verilator reads any "//synopsys full_case" or "//
 synopsys parallel_case" directives.  The same applies to any "//cadence" or
@@ -1052,7 +1107,9 @@ around compiler specific constructs.
 
 =item `verilog
 
-Switch back to processing Verilog code, after a `systemc_... mode switch.
+Switch back to processing Verilog code after a `systemc_... mode switch.
+The Verilog code returns to the last language mode specified with
+`begin_keywords, or SystemVerilog if none were specified.
 
 =item /*verilator clock_enable*/
 
@@ -1075,28 +1132,7 @@ submodules will be named I<submodule>__DOT__I<subsignal> as C++ does not
 allow "." in signal names.  SystemPerl when tracing such signals will
 replace the __DOT__ with the period.
 
-=item /*verilator lint_off I<msg>*/
-
-Disable the specified warning message for any warnings following the comment.
-
-=item /*verilator lint_on I<msg>*/
-
-Re-enable the specified warning message for any warnings following the comment.
-
-=item /*verilator no_inline_task*/ 
-
-Used in a function or task variable definition section to specify the
-function or task should not be inlined into where it is used.  This may
-reduce the size of the final executable when a task is used a very large
-number of times.  For this flag to work, the task and tasks below it must
-be pure; they cannot reference any variables outside the task itself.
-
-=item /*verilator sc_clock*/
-
-Used after a input declaration to indicate the signal should be declared in
-SystemC as a sc_clock instead of a bool.
-
-=item /*verilator isolate_asignments*/
+=item /*verilator isolate_assignments*/
 
 Used after a signal declaration to indicate the assignments to this signal
 in any blocks should be isolated into new blocks.  When there is a large
@@ -1105,7 +1141,7 @@ this to the signal causing a false loop may clear up the problem.
 
 IE, with the following
 
-    reg splitme /* verilator isolate_asignments*/;
+    reg splitme /* verilator isolate_assignments*/;
     always @* begin
       if (....) begin
          splitme = ....;
@@ -1131,21 +1167,48 @@ It would then internally break it into (sort of):
       end
     end
 
-=item /*verilator tracing_off*/
+=item /*verilator lint_off I<msg>*/
 
-Disable waveform tracing for all future signals that are declared in this
-module.  Often this is placed just after a primitive's module statement, so
-that the entire module is not traced.
+Disable the specified warning message for any warnings following the comment.
 
-=item /*verilator tracing_on*/
+=item /*verilator lint_on I<msg>*/
 
-Re-enable waveform tracing for all future signals that are declared.
+Re-enable the specified warning message for any warnings following the comment.
+
+=item /*verilator lint_restore*/
+
+After a /*verilator lint_save*/, pop the stack containing lint message
+state.  Often this is useful at the bottom of include files.
+
+=item /*verilator lint_save*/
+
+Push the current state of what lint messages are turned on or turned off to
+a stack.  Later meta-comments may then lint_on or lint_off specific
+messages, then return to the earlier message state by using /*verilator
+lint_restore*/.  For example:
+
+    // verilator lint_save
+    // verilator lint_off SOME_WARNING
+    ...  // code needing SOME_WARNING turned off
+    // verilator lint_restore
+
+If SOME_WARNING was on before the lint_off, it will now be restored to on,
+and if it was off before the lint_off it will remain off.
+
+=item /*verilator no_inline_task*/ 
+
+Used in a function or task variable definition section to specify the
+function or task should not be inlined into where it is used.  This may
+reduce the size of the final executable when a task is used a very large
+number of times.  For this flag to work, the task and tasks below it must
+be pure; they cannot reference any variables outside the task itself.
 
 =item /*verilator public*/ (variable)
 
 Used after a input, output, register, or wire declaration to indicate the
 signal should be declared so that C code may read or write the value
-of the signal.
+of the signal.  This will also declare this module public, otherwise use
+/*verilator public_flat*/.
 
 =item /*verilator public*/ (task/function)
 
@@ -1167,6 +1230,14 @@ stored state (flops) should be written, as the model will NOT notice
 changes made to variables in these functions.  (Same as when a signal is
 declared public.)
 
+=item /*verilator public_flat*/ (variable)
+
+Used after a input, output, register, or wire declaration to indicate the
+signal should be declared so that C code may read or write the value of the
+signal.  This will not declare this module public, which means the name of
+the signal or path to it may change based upon the module inlining which
+takes place.
+
 =item /*verilator public_module*/
 
 Used after a module statement to indicate the module should not be inlined
@@ -1175,6 +1246,21 @@ Verilator automatically sets this attribute when the module contains any
 public signals or `systemc_ directives.  Also set for all modules when
 using the --public switch.
 
+=item /*verilator sc_clock*/
+
+Used after a input declaration to indicate the signal should be declared in
+SystemC as a sc_clock instead of a bool.
+
+=item /*verilator tracing_off*/
+
+Disable waveform tracing for all future signals that are declared in this
+module.  Often this is placed just after a primitive's module statement, so
+that the entire module is not traced.
+
+=item /*verilator tracing_on*/
+
+Re-enable waveform tracing for all future signals that are declared.
+
 =back
 
 =head1 LANGUAGE LIMITATIONS
@@ -1220,6 +1306,10 @@ users to use these names, so it should not matter.
 If you are having trouble determining where a dotted path goes wrong, note
 that Verilator will print a list of known scopes to help your debugging.
 
+=head2 Floating Point
+
+Floating Point numbers are not synthesizable, and so not supported.
+
 =head2 Latches
 
 Verilator is optimized for edge sensitive (flop based) designs.  It will
@@ -1272,17 +1362,12 @@ prepended.  (If you don't know what this means, Verilator will do what you
 probably expect -- what C does. The default behavior of Verilog is
 different.)
 
-=head2 Generate Statements
-
-All instantiations and variables in generate blocks will be placed under
-hierarchy that has a name different from that required in the language
-specification.
-
 =head2 Generated Clocks
 
 Verilator attempts to deal with generated clocks correctly, however new
 cases may turn up bugs in the scheduling algorithm.  The safest option is
-to have all clocks as primary inputs to the model.
+to have all clocks as primary inputs to the model, or wires directly
+attached to primary inputs.
 
 =head2 Ranges must be big-bit-endian
 
@@ -1332,6 +1417,47 @@ will give a width warning and wrap around the power-of-2 size.  For
 non-power-of-2 sizes, it will return a unspecified constant of the
 appropriate width.
 
+=head2 Assertions
+
+Verilator is beginning to add support for assertions.  Verilator currently
+only converts assertions to simple "if (...) error" statements, and
+coverage statements to increment the line counters described in the
+coverage section.
+
+Verilator does not support SEREs yet.  All assertion and coverage
+statements must be simple expressions that complete in one cycle.
+(Arguably SEREs are much of the point, but one must start somewhere.)
+
+=head1 LANGUAGE KEYWORD LIMITATIONS
+
+This section describes specific limitations for each language keyword.
+
+=over 4
+
+=item always, always_comb, always_ff, always_latch, and, assign, begin,
+buf, case, casex, casez, default, defparam, do-while, else, end, endcase,
+endfunction, endgenerate, endmodule, endspecify, endtask, final, for,
+function, generate, genvar, if, initial, inout, input, integer, localparam,
+macromodule, module, nand, negedge, nor, not, or, output, parameter,
+posedge, reg, scalared, signed, supply0, supply1, task, tri, vectored,
+while, wire, xnor, xor
+
+Generally supported.
+
+=item specify specparam
+
+All specify blocks and timing checks are ignored.
+
+=item uwire
+
+Verilator does not perform warning checking on uwires, it treats the uwire
+keyword as if it were the normal wire keyword.
+
+=item $bits, $countones, $finish, $isunknown, $onehot, $onehot0, $readmemb,
+$readmemh, $signed, $stop, $time, $unsigned
+
+Generally supported.
+
 =item $display, $write, $fdisplay, $fwrite
 
 $display and friends must have a constant format string as the first
@@ -1352,12 +1478,23 @@ are 32 bits while FILE*s may be 64 bits, the descriptor must be stored in a
 reg [63:0] rather then an integer.  The define `verilator_file_descriptor in
 verilated.v can be used to hide this difference.
 
+=item $fullskew, $hold, $nochange, $period, $recovery, $recrem, $removal,
+$setup, $setuphold, $skew, $timeskew, $width
+
+All specify blocks and timing checks are ignored.
+
 =item $readmemb, $readmemh
 
 Read memory commands should work properly.  Note Verilator and the Verilog
 specification does not include support for readmem to multi-dimensional
 arrays.
 
+=item $realtime
+
+Treated as $time.
+
+=back
+
 =head1 ERRORS AND WARNINGS
 
 Warnings may be disabled in two ways.  First, when the warning is
@@ -1380,9 +1517,9 @@ List of all warnings:
 
 =item BLKANDNBLK
 
-Error that a variable comes from a mix of blocked and non-blocking
-assignments.  Generally, this is caused by a register driven by both combo
-logic and a flop:
+BLKANDNBLK is an error that a variable comes from a mix of blocked and
+non-blocking assignments.  Generally, this is caused by a register driven
+by both combo logic and a flop:
 
       always @ (posedge clk)  foo[0] <= ...
       always @* foo[1] = ...
@@ -1398,6 +1535,9 @@ This is good coding practice anyways.
 It is also possible to disable this error when one of the assignments is
 inside a public task.
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item CASEINCOMPLETE
 
 Warns that inside a case statement there is a stimulus pattern for which
@@ -1405,6 +1545,9 @@ there is no case item specified.  This is bad style, if a case is
 impossible, it's better to have a "default: $stop;" or just "default: ;" so
 that any design assumption violations will be discovered in simulation.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CASEOVERLAP
 
 Warns that inside a case statement you have case values which are detected
@@ -1412,17 +1555,26 @@ to be overlapping.  This is bad style, as moving the order of case values
 will cause different behavior.  Generally the values can be respecified to
 not overlap.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CASEX
 
 Warns that it is simply better style to use casez, and C<?> in place of
 C<x>'s.  See
 L<http://www.sunburst-design.com/papers/CummingsSNUG1999Boston_FullParallelCase_rev1_1.pdf>
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item CMPCONST
 
 Warns that you are comparing a value in a way that will always be constant.
 For example "X > 1" will always be true when X is a single bit wide.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item COMBDLY
 
 Warns that you have a delayed assignment inside of a combinatorial block.
@@ -1432,6 +1584,9 @@ Verilator, like synthesis, will convert this to a non-delayed assignment,
 which may result in logic races or other nasties.  See
 L<http://www.sunburst-design.com/papers/CummingsSNUG2000SJ_NBA_rev1_2.pdf>
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item GENCLK
 
 Warns that the specified signal is generated, but is also being used as a
@@ -1442,6 +1597,9 @@ generate ALL clocks outside in C++/SystemC and make them primary inputs to
 your Verilog model.  (However once need to you have even one, don't sweat
 additional ones.)
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item IMPLICIT
 
 Warns that a wire is being implicitly declared (it is a single bit wide
@@ -1451,18 +1609,38 @@ signal before it is implicitly declared by a cell, and can lead to dangling
 nets.  A better option is the /*AUTOWIRE*/ feature of Verilog-Mode for
 Emacs, available from L<http://www.veripool.com/>
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item IMPURE
 
 Warns that a task or function that has been marked with /*verilator
 no_inline_task*/ references variables that are not local to the task.
 Verilator cannot schedule these variables correctly.
 
+Ignoring this warning may make Verilator simulations differ from other
+simulators.
+
 =item MULTIDRIVEN
 
 Warns that the specified signal comes from multiple always blocks.  This is
 often unsupported by synthesis tools, and is considered bad style.  It will
 also cause longer runtimes due to reduced optimizations.
 
+Ignoring this warning will only slow simulations, it will simulate
+correctly.
+
+=item MULTITOP
+
+Error that there are multiple top level modules, that is modules not
+instantiated by any other module.  Verilator only supports a single top
+level, if you need more, create a module that wraps all of the top modules.
+
+Often this error is because some low level cell is being read in, but is
+not really needed.  The best solution is to insure that each module is in a
+unique file by the same name.  Otherwise, make sure all library files are
+read in as libraries with -v, instead of automatically with -y.
+
 =item TASKNSVAR
 
 Error when a call to a task or function has a output from that task tied to
@@ -1490,6 +1668,9 @@ cases would result in simulator mismatches.
 
 Warns that the specified signal is never sourced.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item UNOPT
 
 Warns that due to some construct, optimization of the specified signal or
@@ -1503,6 +1684,9 @@ blocks in both submodules, even if they are unrelated always blocks.  This
 affects performance because Verilator would have to evaluate each submodule
 multiple times to stabilize the signals crossing between the modules.
 
+Ignoring this warning will only slow simulations, it will simulate
+correctly.
+
 =item UNOPTFLAT
 
 Warns that due to some construct, optimization of the specified signal is
@@ -1552,18 +1736,27 @@ clock_enable meta comment described above.
 
 The UNOPTFLAT warning may also occur where outputs from a block of logic
 are independent, but occur in the same always block.  To fix this, use the
-isolate_asignments meta comment described above.
+isolate_assignments meta comment described above.
+
+Ignoring this warning will only slow simulations, it will simulate
+correctly.
 
 =item UNSIGNED
 
 Warns that you are comparing a unsigned value in a way that implies it is
 signed, for example "X < 0" will always be true when X is unsigned.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item UNUSED
 
 Warns that the specified signal is never sinked.  This is a future message,
 currently Verilator will not produce this warning.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item VARHIDDEN
 
 Warns that a task, function, or begin/end block is declaring a variable by
@@ -1571,6 +1764,9 @@ the same name as a variable in the upper level module or begin/end block
 (thus hiding the upper variable from being able to be used.)  Rename the
 variable to avoid confusion when reading the code.
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =item WIDTH
 
 Warns that based on width rules of Verilog, two operands have different
@@ -1589,6 +1785,9 @@ The best fix, which clarifies intent and will also make all tools happy is:
 
 	wire [5:0] plus_one = from[5:0] + 6'd1 + {5'd0,carry[0]};
 
+Ignoring this warning will only suppress the lint check, it will simulate
+correctly.
+
 =back
 
 The following describes the less obvious errors:
@@ -1616,12 +1815,18 @@ For example:
    always @ (b)  a=b
 
 will toggle forever and thus the executable will give the didn't converge
-error to prevent an infinite loop.  To debug this, compile the Verilated
-.cpp files with -DVL_DEBUG, then call Verilated::debug(1) in your main.cpp.
-This will cause each module to print a message when it's invoked.  From
-that it should be obvious what routine(s) are part of the infinite loop.
-Then in Gdb, add a break point at the routine entry point and "print *this"
-on each loop so you can see what variables are changing each invocation.
+error to prevent an infinite loop.
+
+To debug this, run Verilator with --profile-cfuncs.  Run make on the
+generated files with "OPT=-DVL_DEBUG". Then call Verilated::debug(1) in
+your main.cpp.
+
+This will cause each change in a variable to print a message.  Near the
+bottom you'll see the code and variable that causes the problem.  For the
+program above:
+
+        CHANGE: filename.v:1: b
+        CHANGE: filename.v:2: a
 
 =back
 

include/verilated.cpp

@@ -72,7 +72,8 @@ void vl_fatal (const char* filename, int linenum, const char* hier, const char*
 // Random reset -- Only called at init time, so don't inline.
 
 IData VL_RAND32() {
-#ifdef _MSC_VER
+#if defined(_WIN32) && !defined(__CYGWIN__)
+    // Windows doesn't have lrand48(), although Cygwin does.
     return (rand()<<16) | rand();
 #else
     return (lrand48()<<16) | lrand48();

include/verilated.h

@@ -513,10 +513,10 @@ static inline IData VL_COUNTONES_W(int words, WDataInP lwp) {
 }
 
 static inline IData VL_ONEHOT_I(IData lhs) {
-    return ((lhs & (lhs-1))==0 & lhs!=0);
+    return (((lhs & (lhs-1))==0) & (lhs!=0));
 }
 static inline IData VL_ONEHOT_Q(QData lhs) {
-    return ((lhs & (lhs-1))==0 & lhs!=0);
+    return (((lhs & (lhs-1))==0) & (lhs!=0));
 }
 static inline IData VL_ONEHOT_W(int words, WDataInP lwp) {
     IData one=0;

include/verilated.mk.in

@@ -49,7 +49,12 @@ VPATH += $(VERILATOR_ROOT)/include
 CPPFLAGS += $(OPT)
 
 CPPFLAGS += $(M32)
-LDFLAGS += $(M32)
+LDFLAGS  += $(M32)
+
+# Allow upper level user makefiles to specify flags they want.
+# These aren't ever set by Verilator, so users are free to override them.
+CPPFLAGS += $(USER_CPPFLAGS)
+LDFLAGS  += $(USER_LDFLAGS)
 
 # See the benchmarking section of bin/verilator.
 # Support class optimizations.  This includes the tracing and symbol table.
@@ -84,8 +89,8 @@ endif
 ##### SystemPerl builds
 
 ifeq ($(VM_SP),1)
-  CPPFLAGS += -I$(SYSTEMPERL) -I$(SYSTEMPERL)/src -DSYSTEMPERL
-  VPATH    +=   $(SYSTEMPERL)   $(SYSTEMPERL)/src
+  CPPFLAGS += -I$(SYSTEMPERL)/src -DSYSTEMPERL
+  VPATH    +=   $(SYSTEMPERL)/src
 
   VK_CLASSES_SP = $(addsuffix .sp, $(VM_CLASSES))
 
@@ -104,8 +109,8 @@ endif
 ifeq ($(VM_PCLI),1)
   LIBS   += -lm -lstdc++
  ifeq ($(VM_TRACE),1)
-  CPPFLAGS += -I$(SYSTEMPERL) -I$(SYSTEMPERL)/src
-  VPATH    +=   $(SYSTEMPERL)   $(SYSTEMPERL)/src
+  CPPFLAGS += -I$(SYSTEMPERL)/src
+  VPATH    +=   $(SYSTEMPERL)/src
  endif
 endif
 

include/verilatedos.h

@@ -39,6 +39,8 @@
 # define VL_ATTR_UNUSED __attribute__ ((unused))
 # define VL_LIKELY(x)	__builtin_expect(!!(x), 1)
 # define VL_UNLIKELY(x)	__builtin_expect(!!(x), 0)
+# define VL_PREFETCH_RD(p) __builtin_prefetch((p),0)
+# define VL_PREFETCH_RW(p) __builtin_prefetch((p),1)
 #else
 # define VL_ATTR_PRINTF(fmtArgNum)	///< Function with printf format checking
 # define VL_ATTR_ALIGNED(alignment)	///< Align structure to specified byte alignment
@@ -46,6 +48,8 @@
 # define VL_ATTR_UNUSED			///< Function that may be never used
 # define VL_LIKELY(x)	(!!(x))		///< Boolean expression more often true then false
 # define VL_UNLIKELY(x)	(!!(x))		///< Boolean expression more often false then true
+# define VL_PREFETCH_RD(p)		///< Prefetch data with read intent
+# define VL_PREFETCH_RW(p)		///< Prefetch data with read/write intent
 #endif
 
 #ifdef VL_THREADED
@@ -79,7 +83,7 @@ typedef long  			vlsint32_t;	///< 32-bit signed type
 typedef unsigned long           vluint32_t;	///< 32-bit unsigned type
 typedef long long      		vlsint64_t;	///< 64-bit signed type
 typedef unsigned long long      vluint64_t;	///< 64-bit unsigned type
-#elif defined(_WIN32)
+#elif defined(_WIN32) && !defined(__MINGW32__)
 typedef unsigned char           uint8_t;	///< 8-bit unsigned type (backward compatibility)
 typedef unsigned short int      uint16_t;	///< 16-bit unsigned type (backward compatibility)
 typedef unsigned long           uint32_t;	///< 32-bit unsigned type (backward compatibility)

nodist/dot_importer

@@ -0,0 +1,174 @@
+#!/usr/bin/perl -w
+# $Id$
+######################################################################
+#
+# Copyright 2005-2007 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use Getopt::Long;
+use IO::File;
+use Pod::Usage;
+use Data::Dumper; $Data::Dumper::Indent=1;
+use strict;
+use vars qw ($Debug);
+
+#======================================================================
+
+our @Header;
+our %Vertexes;
+our @Edges;
+our %Edges;
+
+#======================================================================
+# main
+
+$Debug = 0;
+my $opt_filename;
+autoflush STDOUT 1;
+autoflush STDERR 1;
+if (! GetOptions (
+		  "help"	=> \&usage,
+		  "debug"	=> \&debug,
+		  "<>"		=> \&parameter,
+		  )) {
+    usage();
+}
+
+dotread ($opt_filename);
+cwrite ("graph_export.cpp");
+
+#----------------------------------------------------------------------
+
+sub usage {
+    print '$Id$ ', "\n";
+    pod2usage(-verbose=>2, -exitval => 2);
+    exit (1);
+}
+
+sub debug {
+    $Debug = 1;
+}
+
+sub parameter {
+    my $param = shift;
+    if (!$opt_filename) {
+	$opt_filename = $param;
+    } else {
+	die "%Error: Unknown parameter: $param\n";
+    }
+}
+
+#######################################################################
+
+sub dotread {
+    my $filename = shift;
+
+    my $fh = IO::File->new($filename) or die "%Error: $! $filename,";
+    my $header = 1;
+    my $vnum = 0;
+    while (defined (my $line = $fh->getline)) {
+	if ($line =~ /^\t([a-zA-Z0-9_]+)\t(.*)$/) {
+	    next if $1 eq 'nTITLE';
+	    $header = 0;
+	    $Vertexes{$1} = {num => $vnum++,
+			     line => $line,
+			     name => $1,};
+	}
+	elsif ($line =~ /^\t([a-zA-Z0-9_]+)\s+->\s+([a-zA-Z0-9_]+)\s+(.*)$/) {
+	    my $from=$1; my $to=$2;
+	    my $weight = 1; $weight = $1 if $line =~ /weight=(\d+)/;
+	    my $cutable = undef; $cutable = $1 if $line =~ /style=(\S+)/;
+	    my $edge =  {num => $vnum++,
+			 line => $line,
+			 weight => $weight,
+			 cutable => $cutable,
+			 from => $from,
+			 to => $to,};
+	    push @Edges, $edge;
+	    $Edges{$from}{$to} = $edge;
+	}
+	elsif ($header) {
+	    push @Header, $line;
+	    print "IGNORE: $line";
+	}
+    }
+}
+
+#######################################################################
+
+sub cwrite {
+    my $filename = shift;
+
+    my $fh = IO::File->new(">$filename") or die "%Error: $! $filename,";
+    $fh->print("void V3GraphTestImport::dotImport() {\n");
+    $fh->print("    DfaGraph* gp = &m_graph;\n");
+    foreach my $ver (sort {$a->{num} <=> $b->{num}} (values %Vertexes)) {
+	$fh->printf("    V3GraphTestVertex* %s = new V3GraphTestVertex(gp, \"%s\");  if (%s) {}\n",
+		    $ver->{name}, $ver->{name}, $ver->{name});
+    }
+    $fh->print("\n");
+    foreach my $edge (@Edges) {
+	$fh->printf("    new V3GraphEdge(gp, %s, %s, %s, %s);\n",
+		    $edge->{from}, $edge->{to},
+		    $edge->{weight}, $edge->{cutable}?"true":"false");	       
+    }
+    $fh->print("}\n");
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+dot_importer - Take graph .dot file and convert into .cpp file
+
+=head1 SYNOPSIS
+
+  dot_importer a.dot
+
+=head1 DESCRIPTION
+
+Dot_importer takes a graphvis .dot file and converts into .cpp file.  This
+.cpp file is then manually included in V3GraphTest.cpp to verify various
+sub-algorithms.
+
+=head1 ARGUMENTS
+
+=over 4
+
+=item --help
+
+Displays this message and program version and exits.
+
+=back
+
+=head1 DISTRIBUTION
+
+Copyright 2005-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./dot_importer | tee ~/d/a.dot"
+### End:

nodist/invoke_ncverilog

@@ -0,0 +1,70 @@
+#!/usr/bin/perl -w
+# $Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder <[email protected]>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use strict;
+
+#======================================================================
+# main
+
+delete $ENV{MODULE_VERSION};
+_setup_modules();
+module('add','cadence_verif');
+exec('ncverilog',@ARGV);
+
+#######################################################################
+# Modules package
+
+sub _setup_modules {
+    # Load the 'module' command into the environment
+    my $init = "/sicortex/$ENV{DIRPROJECT_ARCH}/lib/Modules/default/init/perl";
+    (-f $init) or die "%Error: Script not found: $init,";
+    require $init;
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+invoke_ncverilog - Invoke tool under "modules" command
+
+=head1 SYNOPSIS
+
+  invoke_ncverilog  {ncv arguments}
+
+=head1 DESCRIPTION
+
+=head1 DISTRIBUTION
+
+Copyright 2007-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <[email protected]>
+
+=head1 SEE ALSO
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./invoke_ncverilog -help"
+### End:

src/Makefile_obj.in

@@ -118,6 +118,7 @@ RAW_OBJS = \
 	V3Dead.o \
 	V3Delayed.o \
 	V3Depth.o \
+	V3DepthBlock.o \
 	V3Descope.o \
 	V3EmitC.o \
 	V3EmitCSyms.o \

src/V3Assert.cpp

@@ -47,28 +47,58 @@ private:
     V3Double0	m_statAsCover;	// Statistic tracking
     V3Double0	m_statAsPsl;	// Statistic tracking
     V3Double0	m_statAsFull;	// Statistic tracking
+    V3Double0	m_statAsSV;	// Statistic tracking
 
     // METHODS
-    AstNode* newFireAssert(AstNode* nodep, const string& message) {
-	AstNode* bodysp = new AstDisplay
-	    (nodep->fileline(), '\0',
-	     (string("[%0t] %%Error: ")+nodep->fileline()->filebasename()
-	      +":"+cvtToStr(nodep->fileline()->lineno())
-	      +": Assertion failed in %m"
-	      +((message != "")?": ":"")+message
-	      +"\\n"),
-	     NULL,
-	     new AstTime(nodep->fileline()));
-	bodysp->addNext(new AstStop (nodep->fileline()));
+    string assertDisplayMessage(AstNode* nodep, const string& prefix, const string& message) {
+	return (string("[%0t] "+prefix+": ")+nodep->fileline()->filebasename()
+		+":"+cvtToStr(nodep->fileline()->lineno())
+		+": Assertion failed in %m"
+		+((message != "")?": ":"")+message
+		+"\\n");
+    }
+    void replaceDisplay(AstDisplay* nodep, const string& prefix) {
+	nodep->displayType(AstDisplayType::WRITE);
+	nodep->text(assertDisplayMessage(nodep, prefix, nodep->text()));
+	AstNode* timesp = nodep->exprsp(); if (timesp) timesp->unlinkFrBack();
+	timesp = timesp->addNext(new AstTime(nodep->fileline()));
+	nodep->exprsp(timesp);
+    }
+
+    AstNode* newIfAssertOn(AstNode* nodep) {
 	// Add a internal if to check assertions are on.
 	// Don't make this a AND term, as it's unlikely to need to test this.
-	bodysp = new AstIf (nodep->fileline(),
-			    new AstCMath(nodep->fileline(), "Verilated::assertOn()", 1),
-			    bodysp, NULL);
+	return new AstIf (nodep->fileline(),
+			  // If assertions are off, have constant propagation rip them out later
+			  // This allows syntax errors and such to be detected normally.
+			  (v3Global.opt.assertOn()
+			   ? (AstNode*)(new AstCMath(nodep->fileline(), "Verilated::assertOn()", 1))
+			   : (AstNode*)(new AstConst(nodep->fileline(), V3Number(nodep->fileline(), 1, 0)))),
+			  nodep, NULL);
+    }
+
+    AstNode* newIfCoverageOn(AstNode* nodep) {
+	// Add a internal if to check coverage is on
+	// Don't make this a AND term, as it's unlikely to need to test this.
+	return new AstIf (nodep->fileline(),
+			  // If assertions are off, have constant propagation rip them out later
+			  // This allows syntax errors and such to be detected normally.
+			  (v3Global.opt.coverage()
+			   ? (AstNode*)(new AstConst(nodep->fileline(), V3Number(nodep->fileline(), 1, 1)))
+			   : (AstNode*)(new AstConst(nodep->fileline(), V3Number(nodep->fileline(), 1, 0)))),
+			  nodep, NULL);
+    }
+
+    AstNode* newFireAssert(AstNode* nodep, const string& message) {
+	AstDisplay* dispp = new AstDisplay (nodep->fileline(), AstDisplayType::ERROR, message, NULL, NULL);
+	AstNode* bodysp = dispp;
+	replaceDisplay(dispp, "%%Error");   // Convert to standard DISPLAY format
+	bodysp->addNext(new AstStop (nodep->fileline()));
+	bodysp = newIfAssertOn(bodysp);
 	return bodysp;
     }
 
-    void newAssertion(AstNode* nodep, AstNode* propp, AstSenTree* sentreep, const string& message) {
+    void newPslAssertion(AstNode* nodep, AstNode* propp, AstSenTree* sentreep, const string& message) {
 	propp->unlinkFrBack();
 	sentreep->unlinkFrBack();
 	//
@@ -114,6 +144,28 @@ private:
 	pushDeletep(nodep); nodep=NULL;
     }
 
+    void newVAssertion(AstVAssert* nodep, AstNode* propp) {
+	propp->unlinkFrBackWithNext();
+	AstNode* passsp = nodep->passsp(); if (passsp) passsp->unlinkFrBackWithNext();
+	AstNode* failsp = nodep->failsp(); if (failsp) failsp->unlinkFrBackWithNext();
+	//
+	if (nodep->castVAssert()) {
+	    if (passsp) passsp = newIfAssertOn(passsp);
+	    if (failsp) failsp = newIfAssertOn(failsp);
+	} else {
+	    nodep->v3fatalSrc("Unknown node type");
+	}
+
+	AstIf* ifp = new AstIf (nodep->fileline(), propp, passsp, failsp);
+	AstNode* newp = ifp;
+	if (nodep->castVAssert()) ifp->branchPred(AstBranchPred::UNLIKELY);
+	//
+	// Install it
+	nodep->replaceWith(newp);
+	// Bye
+	pushDeletep(nodep); nodep=NULL;
+    }
+
     // VISITORS  //========== Case assertions
     virtual void visit(AstCase* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
@@ -163,16 +215,34 @@ private:
     }
 
     // VISITORS  //========== Statements
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+	// Replace the special types with standard text
+	if (nodep->displayType()==AstDisplayType::INFO) {
+	    replaceDisplay(nodep, "-Info");
+	} else if (nodep->displayType()==AstDisplayType::WARNING) {
+	    replaceDisplay(nodep, "%%Warning");
+	} else if (nodep->displayType()==AstDisplayType::ERROR
+		   || nodep->displayType()==AstDisplayType::FATAL) {
+	    replaceDisplay(nodep, "%%Error");
+	}
+    }
+
     virtual void visit(AstPslCover* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
-	newAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
+	newPslAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
 	m_statAsCover++;
     }
     virtual void visit(AstPslAssert* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
-	newAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
+	newPslAssertion(nodep, nodep->propp(), nodep->sentreep(), nodep->name()); nodep=NULL;
 	m_statAsPsl++;
     }
+    virtual void visit(AstVAssert* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+	newVAssertion(nodep, nodep->propp()); nodep=NULL;
+	m_statAsSV++;
+    }
 
     virtual void visit(AstModule* nodep, AstNUser*) {
 	m_modp = nodep;
@@ -203,6 +273,7 @@ public:
     }
     virtual ~AssertVisitor() {
 	V3Stats::addStat("Assertions, PSL asserts", m_statAsPsl);
+	V3Stats::addStat("Assertions, SystemVerilog asserts", m_statAsSV);
 	V3Stats::addStat("Assertions, cover statements", m_statAsCover);
 	V3Stats::addStat("Assertions, full/parallel case", m_statAsFull);
     }

src/V3Ast.cpp

@@ -789,7 +789,7 @@ void AstNode::dumpTreeFile(const string& filename, bool append) {
 	    if (logsp->fail()) v3fatalSrc("Can't write "<<filename);
 	    *logsp<<"Tree Dump from <e"<<dec<<editCountLast()<<">";
 	    *logsp<<" to <e"<<dec<<editCountGbl()<<">"<<endl;
-	    if (editCountGbl()==editCountLast() && 0) {  // Off, as messes up tree diffing
+	    if (editCountGbl()==editCountLast() && 1) {  // Off, as messes up tree diffing
 		*logsp<<endl;
 		*logsp<<"No changes since last dump!\n";
 	    } else {

src/V3Ast.h

@@ -250,6 +250,34 @@ public:
 
 //######################################################################
 
+class AstDisplayType {
+public:
+    enum en {
+	DISPLAY,
+	WRITE,
+	INFO,
+	ERROR,
+	WARNING,
+	FATAL
+    };
+    enum en m_e;
+    inline AstDisplayType () {};
+    inline AstDisplayType (en _e) : m_e(_e) {};
+    explicit inline AstDisplayType (int _e) : m_e(static_cast<en>(_e)) {};
+    operator en () const { return m_e; };
+    bool addNewline() const { return m_e!=WRITE; }
+    bool needScopeTracking() const { return m_e!=DISPLAY && m_e!=WRITE; }
+    const char* ascii() const {
+	static const char* names[] = {
+	    "display","write","info","error","warning","fatal"};
+	return names[m_e];};
+  };
+  inline bool operator== (AstDisplayType lhs, AstDisplayType rhs) { return (lhs.m_e == rhs.m_e); }
+  inline bool operator== (AstDisplayType lhs, AstDisplayType::en rhs) { return (lhs.m_e == rhs); }
+  inline bool operator== (AstDisplayType::en lhs, AstDisplayType rhs) { return (lhs == rhs.m_e); }
+
+//######################################################################
+
 class AstParseRefExp {
 public:
     enum en {
@@ -505,6 +533,7 @@ public:
     AstNode*	op3p() const { return m_op3p; }
     AstNode*	op4p() const { return m_op4p; }
     AstNode*	clonep() const { return ((m_cloneCnt==s_cloneCntGbl)?m_clonep:NULL); }
+    AstNode*	firstAbovep() const { return ((backp() && backp()->nextp()!=this) ? backp() : NULL); }  // Returns NULL when second or later in list
     bool	brokeExists() const;
 
     // CONSTRUCTORS
@@ -905,6 +934,7 @@ public:
     virtual ~AstNodePli() {}
     virtual string name()	const { return m_text; }
     virtual int instrCount()	const { return instrCountPli(); }
+    void exprsp(AstNode* nodep)	{ addOp1p(nodep); }	// op1 = Expressions to output
     AstNode* exprsp()		const { return op1p()->castNode(); }	// op1 = Expressions to output
     string 	text()		const { return m_text; }		// * = Text to display
     void text(const string& text) { m_text=text; }

src/V3AstNodes.cpp

@@ -298,6 +298,7 @@ void AstCell::dump(ostream& str) {
     this->AstNode::dump(str);
     if (modp()) { str<<" -> "; modp()->dump(str); }
     else { str<<" ->UNLINKED:"<<modName(); }
+    if (pinStar()) str<<" [.*]";
 }
 void AstCellInline::dump(ostream& str) {
     this->AstNode::dump(str);
@@ -307,6 +308,7 @@ void AstPin::dump(ostream& str) {
     this->AstNode::dump(str);
     if (modVarp()) { str<<" -> "; modVarp()->dump(str); }
     else { str<<" ->UNLINKED"; }
+    if (svImplicit()) str<<" [.SV]";
 }
 void AstVarXRef::dump(ostream& str) {
     this->AstNode::dump(str);

src/V3AstNodes.h

@@ -236,12 +236,13 @@ private:
     bool	m_scClocked:1;	// SystemC sc_clk<> needed
     bool	m_scSensitive:1;// SystemC sensitive() needed
     bool	m_sigPublic:1;	// User C code accesses this signal
+    bool	m_sigModPublic:1;// User C code accesses this signal and module
     bool	m_usedClock:1;	// Signal used as a clock
     bool	m_usedParam:1;	// Parameter is referenced (on link; later signals not setup)
     bool	m_funcLocal:1;	// Local variable for a function
     bool	m_funcReturn:1;	// Return variable for a function
     bool	m_attrClockEn:1;// User clock enable attribute
-    bool	m_attrIsolateAssign:1;// User isolate_asignments attribute
+    bool	m_attrIsolateAssign:1;// User isolate_assignments attribute
     bool	m_fileDescr:1;	// File descriptor
     bool	m_isConst:1;	// Table contains constant data
     bool	m_isStatic:1;	// Static variable
@@ -252,7 +253,8 @@ private:
 	m_primaryIO=false;
 	m_sc=false; m_scClocked=false; m_scSensitive=false;
 	m_usedClock=false; m_usedParam=false;
-	m_sigPublic=false; m_funcLocal=false; m_funcReturn=false; 
+	m_sigPublic=false; m_sigModPublic=false;
+	m_funcLocal=false; m_funcReturn=false; 
 	m_attrClockEn=false; m_attrIsolateAssign=false;
 	m_fileDescr=false; m_isConst=false; m_isStatic=false;
 	m_trace=false;
@@ -307,6 +309,7 @@ public:
     void	usedClock(bool flag) { m_usedClock = flag; }
     void	usedParam(bool flag) { m_usedParam = flag; }
     void	sigPublic(bool flag) { m_sigPublic = flag; }
+    void	sigModPublic(bool flag) { m_sigModPublic = flag; }
     void	sc(bool flag) { m_sc = flag; }
     void	scSensitive(bool flag) { m_scSensitive = flag; }
     void	primaryIO(bool flag) { m_primaryIO = flag; }
@@ -343,6 +346,7 @@ public:
     bool	isScWide() const;
     bool	isScSensitive() const { return m_scSensitive; }
     bool	isSigPublic()  const;
+    bool	isSigModPublic() const { return m_sigModPublic; }
     bool	isTrace() const { return m_trace; }
     bool	isConst() const { return m_isConst; }
     bool	isStatic() const { return m_isStatic; }
@@ -374,6 +378,7 @@ public:
 	propagateAttrFrom(typevarp);
 	combineType(typevarp->varType());
 	if (typevarp->isSigPublic()) sigPublic(true);
+	if (typevarp->isSigModPublic()) sigModPublic(true);
 	if (typevarp->attrScClocked()) attrScClocked(true);
     }
     void	inlineAttrReset(const string& name) {
@@ -571,10 +576,11 @@ private:
     int		m_pinNum;	// Pin number
     string	m_name;		// Pin name, or "" for number based interconnect
     AstVar*	m_modVarp;	// Input/output this pin connects to on submodule.
+    bool	m_svImplicit;	// Pin is SystemVerilog .name'ed
 public:
     AstPin(FileLine* fl, int pinNum, const string& name, AstNode* exprp)
 	:AstNode(fl)
-	,m_name(name) {
+	,m_name(name), m_svImplicit(false) {
 	m_pinNum = pinNum;
 	m_modVarp = NULL;
 	setNOp1p(exprp); }
@@ -591,6 +597,8 @@ public:
     AstNode*	exprp()		const { return op1p()->castNode(); }	// op1 = Expression connected to pin
     AstVar*	modVarp()	const { return m_modVarp; }		// [After Link] Pointer to variable
     void  	modVarp(AstVar* varp) { m_modVarp=varp; }
+    bool	svImplicit()	const { return m_svImplicit; }
+    void        svImplicit(bool flag) { m_svImplicit=flag; }
 };
 
 struct AstModule : public AstNode {
@@ -647,12 +655,14 @@ private:
     string	m_name;		// Cell name
     string	m_origName;	// Original name before dot addition
     string	m_modName;	// Module the cell instances
+    bool	m_pinStar;	// Pin list has .*
     AstModule*	m_modp;		// [AfterLink] Pointer to module instanced
 public:
     AstCell(FileLine* fl, const string& instName, const string& modName,
 	    AstPin* pinsp, AstPin* paramsp, AstRange* rangep)
 	: AstNode(fl)
-	  , m_name(instName), m_origName(instName), m_modName(modName), m_modp(NULL) {
+	, m_name(instName), m_origName(instName), m_modName(modName)
+	, m_pinStar(false), m_modp(NULL) {
 	addNOp1p(pinsp); addNOp2p(paramsp); setNOp3p(rangep); }
     virtual ~AstCell() {}
     virtual AstType type() const { return AstType::CELL;}
@@ -669,6 +679,8 @@ public:
     void origName(const string& name) 	{ m_origName = name; }
     string modName()		const { return m_modName; }		// * = Instance name
     void modName(const string& name)	{ m_modName = name; }
+    bool pinStar()		const { return m_pinStar; }
+    void pinStar(bool flag)		{ m_pinStar = flag; }
     AstPin* pinsp()		const { return op1p()->castPin(); }	// op1 = List of cell ports
     AstPin* paramsp()		const { return op2p()->castPin(); }	// op2 = List of parameter #(##) values
     AstRange* rangep()		const { return op3p()->castRange(); }	// op3 = Range of arrayed instants (NULL=not ranged)
@@ -814,10 +826,13 @@ struct AstTask : public AstNodeFTask {
 };
 
 struct AstFunc : public AstNodeFTask {
+    bool	m_attrIsolateAssign:1;// User isolate_assignments attribute
+public:
     // A function inside a module
     AstFunc(FileLine* fl, const string& name, AstNode* stmtp, AstNode* fvarsp)
 	:AstNodeFTask(fl, name, stmtp) {
 	addNOp1p(fvarsp);
+	m_attrIsolateAssign = false;
     }
     virtual ~AstFunc() {}
     virtual AstType type() const { return AstType::FUNC;}
@@ -826,6 +841,8 @@ struct AstFunc : public AstNodeFTask {
     // op1 = Range output variable (functions only)
     AstNode*	fvarp() 	const { return op1p()->castNode(); }
     void addFvarp(AstNode* nodep) { addOp1p(nodep); }
+    void	attrIsolateAssign(bool flag) { m_attrIsolateAssign = flag; }
+    bool	attrIsolateAssign() const { return m_attrIsolateAssign; }
 };
 
 struct AstTaskRef : public AstNodeFTaskRef {
@@ -1226,19 +1243,19 @@ struct AstDisplay : public AstNodePli {
     // Parents: stmtlist
     // Children: file which must be a varref, MATH to print
 private:
-    char	m_newline;
+    AstDisplayType	m_displayType;
 public:
-    AstDisplay(FileLine* fileline, char newln, const string& text, AstNode* filep, AstNode* exprsp)
+    AstDisplay(FileLine* fileline, AstDisplayType dispType, const string& text, AstNode* filep, AstNode* exprsp)
 	: AstNodePli (fileline, text, exprsp) {
 	setNOp2p(filep);
-	m_newline = newln;
+	m_displayType = dispType;
     }
     virtual ~AstDisplay() {}
     virtual AstType type() const { return AstType::DISPLAY;}
     virtual AstNode* clone() { return new AstDisplay(*this); }
     virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
-    virtual string verilogKwd() const { return (filep() ? ((newline() == '\n')?"$fdisplay":"$fwrite")
-						: ((newline() == '\n')?"$display":"$write")); };
+    virtual string verilogKwd() const { return (filep() ? (string)"$f"+(string)displayType().ascii()
+						: (string)"$"+(string)displayType().ascii()); }
     virtual bool isGateOptimizable() const { return false; }
     virtual bool isPredictOptimizable() const { return false; }
     virtual bool isSplittable() const { return false; }	// SPECIAL: $display has 'visual' ordering
@@ -1246,15 +1263,19 @@ public:
     virtual bool isUnlikely() const { return true; }
     virtual V3Hash sameHash() const { return V3Hash(text()); }
     virtual bool same(AstNode* samep) const {
-	return newline()==samep->castDisplay()->newline()
+	return displayType()==samep->castDisplay()->displayType()
 	    && text()==samep->castDisplay()->text(); }
     // op1 used by AstNodePli
-    char	newline()	const { return m_newline; }		// * = Add a newline for $display
+    AstDisplayType	displayType()	const { return m_displayType; }
+    void	displayType(AstDisplayType type) { m_displayType = type; }
+    bool	addNewline() const { return displayType().addNewline(); }  // * = Add a newline for $display
     AstNode*	filep() const { return op2p(); }
     void 	filep(AstNodeVarRef* nodep) { setNOp2p(nodep); }
     AstNode*	scopeAttrp() const { return op3p(); }
     AstText*	scopeTextp() const { return op3p()->castText(); }
     void scopeAttrp(AstNode* nodep) { addOp3p(nodep); }
+    bool	needScopeTracking() { return (displayType().needScopeTracking()
+					      || name().find("%m") != string::npos); }
 };
 
 struct AstFClose : public AstNodeStmt {
@@ -2606,6 +2627,30 @@ struct AstReplicate : public AstNodeBiop {
     virtual int instrCount()	const { return widthInstrs()*2; }
 };
 
+//======================================================================
+// SysVerilog assertions
+
+struct AstVAssert : public AstNodeStmt {
+    // Verilog Assertion
+    // Parents:  {statement list}
+    // Children: expression, if pass statements, if fail statements
+    AstVAssert(FileLine* fl, AstNode* propp, AstNode* passsp, AstNode* failsp)
+	: AstNodeStmt(fl) {
+	addOp1p(propp);
+	addNOp2p(passsp);
+	addNOp3p(failsp);
+    }
+    virtual ~AstVAssert() {}
+    virtual AstType type() const { return AstType::VASSERT;}
+    virtual AstNode* clone() { return new AstVAssert(*this); }
+    virtual void accept(AstNVisitor& v, AstNUser* vup=NULL) { v.visit(this,vup); }
+    virtual V3Hash sameHash() const { return V3Hash(); }
+    virtual bool same(AstNode* samep) const { return true; }
+    AstNode*	propp()		const { return op1p(); }	// op1 = property
+    AstNode*	passsp()	const { return op2p(); }	// op2 = if passes
+    AstNode*	failsp()	const { return op3p(); }	// op3 = if fails
+};
+
 //======================================================================
 // PSL
 

src/V3Begin.cpp

@@ -131,6 +131,18 @@ private:
 	nodep->replaceWith(newp);
 	nodep->deleteTree(); nodep=NULL;
     }
+    virtual void visit(AstDisplay* nodep, AstNUser*) {
+	// If there's a %m in the display text, we add a special node that will contain the name()
+	// Similar code in V3Inline
+	if (m_beginScope != "" && nodep->needScopeTracking()) {
+	    // To keep correct visual order, must add before other Text's
+	    AstNode* afterp = nodep->scopeAttrp();
+	    if (afterp) afterp->unlinkFrBackWithNext();
+	    nodep->scopeAttrp(new AstText(nodep->fileline(), (string)"."+AstNode::prettyName(m_beginScope)));
+	    if (afterp) nodep->scopeAttrp(afterp);
+	}
+	nodep->iterateChildren(*this);
+    }
     virtual void visit(AstNode* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
     }

src/V3Clean.cpp

@@ -104,11 +104,8 @@ private:
 	nodep->unlinkFrBack(&relinkHandle);
 	//
 	computeCppWidth(nodep);
-	V3Number zero (nodep->fileline(), nodep->widthMin(),0);
-	V3Number masksmall (nodep->fileline(), nodep->widthMin());
-	masksmall.opNot(zero);
 	V3Number mask (nodep->fileline(), cppWidth(nodep));
-	mask.opAssign(masksmall);
+	mask.setMask(nodep->widthMin());
 	AstNode* cleanp = new AstAnd (nodep->fileline(),
 				      new AstConst (nodep->fileline(), mask),
 				      nodep);

src/V3Clock.cpp

@@ -472,7 +472,8 @@ private:
 	ifstmtp->addNext(new AstIf(fl,
 				   new AstLt (fl, new AstConst(fl, 100),
 					      new AstVarRef(fl, countVarp, false)),
-				   (new AstDisplay (fl, '\n', "%%Error: Verilated model didn't converge", NULL, NULL))
+				   (new AstDisplay (fl, AstDisplayType::DISPLAY,
+						    "%%Error: Verilated model didn't converge", NULL, NULL))
 				   ->addNext(new AstStop (fl)),
 				   NULL));
 	untilp->addBodysp(new AstIf(fl, new AstNeq(fl, new AstConst(fl, 0),

src/V3Const.cpp

@@ -246,9 +246,8 @@ private:
 	replaceNum(nodep, 0); nodep=NULL;
     }
     void replaceAllOnes (AstNode* nodep) {
-	V3Number num (nodep->fileline(), nodep->width(), 0);
-	V3Number ones (nodep->fileline(), nodep->width());
-	ones.opNot(num);
+	V3Number ones (nodep->fileline(), nodep->width(), 0);
+	ones.setMask(nodep->width());
 	replaceNum(nodep, ones); nodep=NULL;
     }
     void replaceConst(AstNodeUniop* nodep) {
@@ -388,7 +387,7 @@ private:
 	    AstNode* newp;
 	    V3Number mask1 (nodep->fileline(), nodep->width());
 	    V3Number ones (nodep->fileline(), nodep->width());
-	    ones.opNot(mask1);
+	    ones.setMask(nodep->width());
 	    if (shift1<0) {
 		mask1.opShiftR(ones,V3Number(nodep->fileline(),VL_WORDSIZE,-shift1));
 	    } else {
@@ -757,7 +756,8 @@ private:
 	    nodep->varp()->initp()->iterateAndNext(*this);
 	    if (operandConst(nodep->varp()->initp())
 		&& !nodep->lvalue()
-		&& ((v3Global.opt.oConst() && !m_params) // Can reduce constant wires into equations
+		&& ((v3Global.opt.oConst() && !m_params // Can reduce constant wires into equations
+		     && !nodep->varp()->isSigPublic())
 		    || nodep->varp()->isParam())) {
 		AstConst* constp = nodep->varp()->initp()->castConst();
 		const V3Number& num = constp->num();

src/V3Depth.cpp

@@ -40,7 +40,6 @@
 #include "V3Ast.h"
 
 //######################################################################
-// Depth state, as a visitor of each AstNode
 
 class DepthVisitor : public AstNVisitor {
 private:
@@ -55,11 +54,6 @@ private:
 
     //int debug() { return 9; }
 
-    // MSVC++ has a limit of 100 parenthesis.  We have some operator
-    // defines that use 2 parens.  Thus we can't have a expression deeper
-    // then 50 operators.  We'll add some margin though.
-    enum en { MAX_EXPR_DEPTH = 40 };	// Expressions deeper then this need temp
-
     // METHODS
     void createDeepTemp(AstNode* nodep) {
 	UINFO(6,"  Deep  "<<nodep<<endl);
@@ -114,13 +108,15 @@ private:
     virtual void visit(AstNodeTermop* nodep, AstNUser*) {
     }
     virtual void visit(AstNodeMath* nodep, AstNUser*) {
-	m_depth++;
+	// We have some operator defines that use 2 parens, so += 2.
+	m_depth += 2;
 	if (m_depth>m_maxdepth) m_maxdepth=m_depth;
 	nodep->iterateChildren(*this); 
-	m_depth--;
+	m_depth -= 2;
 
-	if ((m_maxdepth-m_depth) > MAX_EXPR_DEPTH
-	    && m_stmtp
+	if (m_stmtp
+	    && (v3Global.opt.compLimitParens() >= 1)	// Else compiler doesn't need it
+	    && (m_maxdepth-m_depth) > v3Global.opt.compLimitParens()
 	    && !nodep->backp()->castNodeStmt()  // Not much point if we're about to use it
 	    ) {
 	    m_maxdepth = m_depth;
@@ -173,14 +169,10 @@ public:
     virtual ~DepthVisitor() {}
 };
 
-//----------------------------------------------------------------------
-// Top loop
-
 //######################################################################
 // Depth class functions
 
 void V3Depth::depthAll(AstNetlist* nodep) {
     UINFO(2,__FUNCTION__<<": "<<endl);
-    // We must do it in bottom-up module
     DepthVisitor visitor (nodep);
 }

src/V3DepthBlock.cpp

@@ -0,0 +1,139 @@
+// $Id$
+//*************************************************************************
+// DESCRIPTION: Verilator: Prevent very deep expressions
+//
+// Code available from: http://www.veripool.com/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+// V3DepthBlock's Transformations:
+//		
+// Each module:
+//	For each deep block, create cfunc including that block.
+//
+//*************************************************************************
+
+#include "config_build.h"
+#include "verilatedos.h"
+#include <stdio.h>
+#include <stdarg.h>
+#include <unistd.h>
+#include <algorithm>
+
+#include "V3Global.h"
+#include "V3DepthBlock.h"
+#include "V3Ast.h"
+#include "V3EmitCBase.h"
+
+//######################################################################
+
+class DepthBlockVisitor : public AstNVisitor {
+private:
+    // NODE STATE
+
+    // STATE
+    AstModule*		m_modp;		// Current module
+    AstCFunc*		m_funcp;	// Current function
+    int			m_depth;	// How deep in an expression
+    int			m_deepNum;	// How many functions made
+
+    //int debug() { return 9; }
+
+    // METHODS
+    AstCFunc* createDeepFunc(AstNode* nodep) {
+	AstNRelinker relinkHandle;
+	nodep->unlinkFrBack(&relinkHandle);
+	// Create function
+	string name = m_funcp->name()+"__deep"+cvtToStr(++m_deepNum);
+	AstCFunc* funcp = new AstCFunc(nodep->fileline(), name, NULL);
+	funcp->argTypes(EmitCBaseVisitor::symClassVar());
+	funcp->symProlog(true);
+	funcp->slow(m_funcp->slow());
+	funcp->addStmtsp(nodep);
+	m_modp->addStmtp(funcp);
+	// Call it at the point where the body was removed from
+	AstCCall* callp = new AstCCall(nodep->fileline(), funcp);
+	callp->argTypes("vlSymsp");
+	UINFO(6,"      New "<<callp<<endl);
+	//
+	relinkHandle.relink(callp);
+	return funcp;
+    }
+
+    // VISITORS
+    virtual void visit(AstModule* nodep, AstNUser*) {
+	UINFO(4," MOD   "<<nodep<<endl);
+	m_modp = nodep;
+	m_deepNum = 0;
+	nodep->iterateChildren(*this);
+    }
+    virtual void visit(AstCFunc* nodep, AstNUser*) {
+	// We recurse into this.
+	int lastDepth = m_depth;
+	AstCFunc* lastFuncp = m_funcp;
+	{
+	    m_depth = 0;
+	    m_funcp = nodep;
+	    nodep->iterateChildren(*this);
+	}
+	m_depth = lastDepth;
+	m_funcp = lastFuncp;
+    }
+    void visitStmt(AstNodeStmt* nodep) {
+	m_depth++;
+	if (m_depth > v3Global.opt.compLimitBlocks()
+	    && !nodep->castCCall()) {   // Already done
+	    UINFO(4, "DeepBlocks "<<m_depth<<" "<<nodep<<endl);
+	    AstNode* backp = nodep->backp();  // Only for debug
+	    if (debug()>=9) backp->dumpTree(cout,"-   pre : ");
+	    AstCFunc* funcp = createDeepFunc(nodep);
+	    funcp->accept(*this);
+	    if (debug()>=9) backp->dumpTree(cout,"-   post: ");
+	    if (debug()>=9) funcp->dumpTree(cout,"-   func: ");
+	} else {
+	    nodep->iterateChildren(*this);
+	}
+	m_depth--;
+    }
+    virtual void visit(AstNodeStmt* nodep, AstNUser*) {
+	visitStmt(nodep);
+    }
+
+    virtual void visit(AstNodeMath* nodep, AstNUser*) {}  // Accelerate
+    //--------------------
+    // Default: Just iterate
+    virtual void visit(AstVar* nodep, AstNUser*) {}	// Don't hit varrefs under vars
+    virtual void visit(AstNode* nodep, AstNUser*) {
+	nodep->iterateChildren(*this);
+    }
+
+public:
+    // CONSTUCTORS
+    DepthBlockVisitor(AstNode* nodep) {
+	m_modp=NULL;
+	m_depth=0;
+	//
+	nodep->accept(*this);
+    }
+    virtual ~DepthBlockVisitor() {}
+};
+
+//######################################################################
+// DepthBlock class functions
+
+void V3DepthBlock::depthBlockAll(AstNetlist* nodep) {
+    UINFO(2,__FUNCTION__<<": "<<endl);
+    DepthBlockVisitor visitor (nodep);
+}

src/V3DepthBlock.h

@@ -0,0 +1,36 @@
+// $Id$ //-*- C++ -*-
+//*************************************************************************
+// DESCRIPTION: Verilator: Prevent very deep expressions
+//
+// Code available from: http://www.veripool.com/verilator
+//
+// AUTHORS: Wilson Snyder with Paul Wasson, Duane Gabli
+//
+//*************************************************************************
+//
+// Copyright 2003-2007 by Wilson Snyder.  This program is free software; you can
+// redistribute it and/or modify it under the terms of either the GNU
+// General Public License or the Perl Artistic License.
+//
+// Verilator is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+// GNU General Public License for more details.
+//
+//*************************************************************************
+
+#ifndef _V3DEPTHBLOCK_H_
+#define _V3DEPTHBLOCK_H_ 1
+#include "config_build.h"
+#include "verilatedos.h"
+#include "V3Error.h"
+#include "V3Ast.h"
+
+//============================================================================
+
+class V3DepthBlock {
+public:
+    static void depthBlockAll(AstNetlist* nodep);
+};
+
+#endif // Guard

src/V3Descope.cpp

@@ -160,8 +160,8 @@ private:
 		    }
 		}
 		// Not really any way the user could do this, and we'd need to come up with some return value
-		//newfuncp->addStmtsp(new AstDisplay (newfuncp->fileline(),
-		//				    '\n', string("%%Error: ")+name+"() called with bad scope", NULL));
+		//newfuncp->addStmtsp(new AstDisplay (newfuncp->fileline(), AstDisplayType::DISPLAY,
+		//				      string("%%Error: ")+name+"() called with bad scope", NULL));
 		//newfuncp->addStmtsp(new AstStop (newfuncp->fileline()));
 		if (debug()>=9) newfuncp->dumpTree(cout,"   newfunc: ");
 	    } else {

src/V3EmitC.cpp

@@ -594,7 +594,14 @@ class EmitCImp : EmitCStmts {
 	if (filenum) filenameNoExt += "__"+cvtToStr(filenum);
 	filenameNoExt += (slow ? "__Slow":"");
 	V3OutCFile* ofp = NULL;
-	if (optSystemPerl()) {
+	if (v3Global.opt.lintOnly()) {
+	    // Unfortunately we have some lint checks here, so we can't just skip processing.
+	    // We should move them to a different stage.
+	    string filename = "/dev/null";
+	    newCFile(filename, slow, source);
+	    ofp = new V3OutSpFile (filename);
+	}
+	else if (optSystemPerl()) {
 	    string filename = filenameNoExt+".sp";
 	    newCFile(filename, slow, source);
 	    ofp = new V3OutSpFile (filename);
@@ -687,6 +694,21 @@ class EmitCImp : EmitCStmts {
 	if (gotOne) {
 	    puts(");\n");
 	    //puts("VL_DEBUG_IF( if (__req) cout<<\"\tCLOCKREQ );");
+	    for (vector<AstChangeDet*>::iterator it = m_blkChangeDetVec.begin();
+		 it != m_blkChangeDetVec.end(); ++it) {
+		AstChangeDet* nodep = *it;
+		if (nodep->lhsp()) {
+		    puts("VL_DEBUG_IF( if(__req && (");
+		    bool gotOneIgnore = false;
+		    doubleOrDetect(nodep, gotOneIgnore);
+		    string varname;
+		    if (nodep->lhsp()->castVarRef()) {
+			varname = ": "+nodep->lhsp()->castVarRef()->varp()->prettyName();
+		    }
+		    puts(")) cout<<\"\tCHANGE: "+nodep->fileline()->ascii()
+			 +varname+"\"<<endl; );");
+		}
+	    }
 	}
     }
 
@@ -998,7 +1020,6 @@ void EmitCStmts::displayArg(AstDisplay* dispp, AstNode** elistp, string fmt, cha
 
 void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
     string vformat = nodep->text();
-    bool addNewline = (nodep->newline() == '\n');
     AstNode* elistp = nodep->exprsp();
 
     // Convert Verilog display to C printf formats
@@ -1061,7 +1082,7 @@ void EmitCStmts::visit(AstDisplay* nodep, AstNUser*) {
     if (elistp != NULL) {
 	nodep->v3error("Extra arguments for $display format\n");
     }
-    if (addNewline) emitDispState.pushFormat("\\n");
+    if (nodep->addNewline()) emitDispState.pushFormat("\\n");
     displayEmit(nodep);
 }
 

src/V3EmitMk.cpp

@@ -138,7 +138,7 @@ public:
 
 	    of.puts("\n# Link rules...\n");
 	    of.puts(v3Global.opt.prefix()+": $(VK_USER_OBJS) $(SP_SRCS) $(VM_PREFIX)__ALL.a\n");
-	    of.puts("\t$(CXX) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt\n");
+	    of.puts("\t$(LINK) $(LDFLAGS) $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt\n");
 	    of.puts("\n");
 	}
 

src/V3Error.h

@@ -37,6 +37,7 @@ public:
 	FATAL,		// Kill the program
 	ERROR,		// General error out, can't suppress
 	// Error codes:
+	MULTITOP,	// Error: Multiple top level modules
 	TASKNSVAR,	// Error: Task I/O not simple
 	// Warning codes:
 	FIRST_WARN,	// Just a code so the program knows where to start warnings
@@ -71,7 +72,7 @@ public:
 	const char* names[] = {
 	    // Leading spaces indicate it can't be disabled.
 	    " SUPPRESS", " FATAL", " ERROR",
-	    "TASKNSVAR",
+	     "MULTITOP", "TASKNSVAR",
 	    " FIRST_WARN",
 	    "BLKANDNBLK",
 	    "CASEINCOMPLETE", "CASEOVERLAP", "CASEX", "CMPCONST",
@@ -197,7 +198,8 @@ public:
     void warnOff(V3ErrorCode code, bool flag) { m_warnOff.set(code,flag); }	// Turn on/off warning messages on this line.
     bool warnOff(const string& code, bool flag);  // Returns 1 if ok
     bool warnIsOff(V3ErrorCode code);
-    void warnResetDefault() { m_warnOff=s_defaultFileLine.m_warnOff; }
+    void warnStateFrom(const FileLine& from) { m_warnOff=from.m_warnOff; }
+    void warnResetDefault() { warnStateFrom(s_defaultFileLine); }
 
     void	v3errorEnd(ostringstream& str);
     inline bool operator==(FileLine rhs) { return (m_lineno==rhs.m_lineno && m_filename==rhs.m_filename); }

src/V3Expand.cpp

@@ -65,11 +65,8 @@ private:
 	if (nodep->isWide()) {
 	    return V3Number (nodep->fileline(), VL_WORDSIZE, VL_MASK_I(nodep->widthMin()));
 	} else {
-	    V3Number zero (nodep->fileline(), nodep->widthMin(),0);
-	    V3Number masksmall (nodep->fileline(), nodep->widthMin());
-	    masksmall.opNot(zero);
 	    V3Number mask (nodep->fileline(), longOrQuadWidth(nodep));
-	    mask.opAssign(masksmall);
+	    mask.setMask(nodep->widthMin());
 	    return mask;
 	}
     }

src/V3Gate.cpp

@@ -198,10 +198,18 @@ public:
 	m_substTreep = NULL;
 	m_buffersOnly = buffersOnly;
 	m_lhsVarRef = NULL;
+	// Iterate
 	nodep->accept(*this);
+	// Check results
 	if (!m_substTreep) {
 	    clearSimple("No assignment found\n");
 	}
+	for (GateVarRefList::const_iterator it = rhsVarRefs().begin();
+	     it != rhsVarRefs().end(); ++it) {
+	    if (m_lhsVarRef && m_lhsVarRef->varScopep() == (*it)->varScopep()) {
+		clearSimple("Circular logic\n");  // Oh my, we'll get a UNOPTFLAT much later.
+	    }
+	}
 	if (debug()>=9 && !m_isSimple) {
 	    nodep->dumpTree(cout,"\tgate!Ok: ");
 	}
@@ -224,6 +232,7 @@ private:
     //Entire netlist:
     // AstVarScope::userp	-> GateVarVertex* for usage var, 0=not set yet
     // {statement}Node::userp	-> GateLogicVertex* for this statement
+
     // STATE
     V3Graph		m_graph;	// Scoreboard of var usages/dependencies
     GateLogicVertex*	m_logicVertexp;	// Current statement being tracked, NULL=ignored
@@ -458,6 +467,7 @@ void GateVisitor::optimizeSignals(bool allowMultiIn) {
 			    }
 			}
 		    }
+		    // Process it
 		    if (!doit) {
 			if (allowMultiIn && (debug()>=9)) {
 			    UINFO(9, "Not ok simp"<<okVisitor.isSimple()<<" mi"<<multiInputs

src/V3Graph.cpp

@@ -180,6 +180,7 @@ void V3Graph::userClearVertices() {
     // the extra code on each read of user() would probably slow things down more then help.
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	vertexp->user(0);
+	vertexp->userp(NULL);	 // Its a union, but might be different size then user()
     }
 }
 
@@ -187,7 +188,8 @@ void V3Graph::userClearEdges() {
     // Clear user() in all of tree
     for (V3GraphVertex* vertexp = verticesBeginp(); vertexp; vertexp=vertexp->verticesNextp()) {
 	for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
-	    edgep->userp(NULL);
+	    edgep->user(0);
+	    edgep->userp(NULL);	 // Its a union, but might be different size then user()
 	}
     }
 }
@@ -253,6 +255,8 @@ void V3Graph::dumpDotFile(const string& filename, bool colorAsSubgraph) {
     *logp<<"digraph v3graph {\n";
     *logp<<"\trankdir="<<dotRankDir()<<"\n";
     *logp<<"\tsize="<<"\"7.5,10\""<<"\n";
+    *logp<<"\tnTITLE\t[fontsize=20 label=\""<<filename<<"\", shape=box, style=bold, color=black];\n";
+    *logp<<"\n";
 
     // List of all possible subgraphs
     typedef multimap<string,V3GraphVertex*> SubgraphMmap;

src/V3GraphAcyc.cpp

@@ -37,6 +37,7 @@
 //	Break the minimal number of backward edges to make the graph acyclic
 
 class GraphAcycVertex : public V3GraphVertex {
+    // user() is used for various sub-algorithm pieces
     V3GraphVertex*	m_origVertexp;		// Pointer to first vertex this represents
 protected:
     friend class GraphAcyc;
@@ -308,6 +309,9 @@ void GraphAcyc::simplifyOne (GraphAcycVertex* avertexp) {
 	    avertexp->setDelete();	// Mark so we won't delete it twice
 	    // Make a new edge connecting the two vertices directly
 	    // If both are breakable, we pick the one with less weight, else it's arbitrary
+	    // We can forget about the origEdge list for the "non-selected" set of edges,
+	    // as we need to break only one set or the other set of edges, not both.
+	    // (This is why we must give preference to the cutable set.)
 	    V3GraphEdge* templateEdgep = ( (inEdgep->cutable()
 					    && (!outEdgep->cutable()
 						|| inEdgep->weight()<outEdgep->weight() ))
@@ -353,7 +357,7 @@ void GraphAcyc::simplifyDup (GraphAcycVertex* avertexp) {
     if (avertexp->isDelete()) return;
     // Clear marks
     for (V3GraphEdge* edgep = avertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
-	edgep->top()->user(false);
+	edgep->top()->userp(NULL);
     }
     // Mark edges and detect duplications
     for (V3GraphEdge* nextp, *edgep = avertexp->outBeginp(); edgep; edgep=nextp) {
@@ -364,16 +368,16 @@ void GraphAcyc::simplifyDup (GraphAcycVertex* avertexp) {
 	    if (!prevEdgep->cutable()) {
 		// !cutable duplicates prev !cutable: we can ignore it, redundant
 		//  cutable duplicates prev !cutable: know it's not a relevant loop, ignore it
-		UINFO(8,"    DelDupEdge "<<avertexp<<endl);
+		UINFO(8,"    DelDupEdge "<<avertexp<<" -> "<<edgep->top()<<endl);
 		edgep->unlinkDelete(); edgep = NULL;
 	    } else if (!edgep->cutable()) {
 		// !cutable duplicates prev  cutable: delete the earlier cutable
-		UINFO(8,"    DelDupPrev "<<avertexp<<endl);
+		UINFO(8,"    DelDupPrev "<<avertexp<<" -> "<<prevEdgep->top()<<endl);
 		prevEdgep->unlinkDelete(); prevEdgep = NULL;
 		outVertexp->userp(edgep);
 	    } else {
 		//  cutable duplicates prev  cutable: combine weights
-		UINFO(8,"    DelDupComb "<<avertexp<<endl);
+		UINFO(8,"    DelDupComb "<<avertexp<<" -> "<<edgep->top()<<endl);
 		prevEdgep->weight (prevEdgep->weight() + edgep->weight());
 		addOrigEdgep (prevEdgep, edgep);
 		edgep->unlinkDelete(); edgep = NULL;

src/V3GraphAlg.cpp

@@ -86,7 +86,7 @@ private:
     void vertexIterate(V3GraphVertex* vertexp) {
 	// Clear marks
 	for (V3GraphEdge* edgep = vertexp->outBeginp(); edgep; edgep=edgep->outNextp()) {
-	    edgep->top()->user(false);
+	    edgep->top()->userp(NULL);
 	}
 	// Mark edges and detect duplications
 	for (V3GraphEdge* nextp, *edgep = vertexp->outBeginp(); edgep; edgep=nextp) {

src/V3GraphTest.cpp

@@ -311,6 +311,34 @@ public:
 	gp->dfaReduce();
     }
 };
+
+//======================================================================
+
+class V3GraphTestImport : public V3GraphTest {
+
+    void dotImport();
+
+public:
+    virtual string name() { return "import"; }
+    virtual void runTest() {
+	DfaGraph* gp = &m_graph;
+	if (V3GraphTest::debug()) gp->debug(9);
+	dotImport();
+	dump();
+	gp->acyclic(&V3GraphEdge::followAlwaysTrue);
+	dump();
+	gp->rank(&V3GraphEdge::followAlwaysTrue);
+	dump();
+    }
+};
+
+#if 0
+# include "graph_export.cpp"
+#else 
+void V3GraphTestImport::dotImport() {
+}
+#endif
+
 //======================================================================
 
 void V3Graph::test() {
@@ -320,5 +348,6 @@ void V3Graph::test() {
     { V3GraphTestAcyc test; test.run(); }
     { V3GraphTestVars test; test.run(); }
     { V3GraphTestDfa test; test.run(); }
+    { V3GraphTestImport test; test.run(); }
     if (V3GraphTest::debug()) v3fatalSrc("Exiting due to graph testing enabled");
 }

src/V3Inline.cpp

@@ -235,8 +235,8 @@ private:
     }
     virtual void visit(AstDisplay* nodep, AstNUser*) {
 	// If there's a %m in the display text, we add a special node that will contain the name()
-	if (m_cellp
-	    && nodep->name().find("%m") != string::npos) {
+	// Similar code in V3Begin
+	if (m_cellp && nodep->needScopeTracking()) {
 	    // To keep correct visual order, must add before other Text's
 	    AstNode* afterp = nodep->scopeAttrp();
 	    if (afterp) afterp->unlinkFrBackWithNext();

src/V3Link.cpp

@@ -143,6 +143,13 @@ private:
 	if (!m_curVarsp) nodep->v3fatalSrc("Var not under module??\n");
 	nodep->iterateChildren(*this);
 	if (m_idState==ID_FIND) {
+	    // We used modTrace before leveling, and we may now
+	    // want to turn it off now that we know the levelizations
+	    if (v3Global.opt.traceDepth()
+		&& (m_modp->level()-1) > v3Global.opt.traceDepth()) {
+		m_modp->modTrace(false);
+		nodep->trace(false);
+	    }
 	    // Find under either a task or the module's vars
 	    AstNode* findidp = m_curVarsp->findIdName(nodep->name());
 	    AstVar* findvarp = findidp->castVar();
@@ -213,6 +220,8 @@ private:
 		nodep->userp(m_curVarsp);
 	    }
 	    // Convert the func's range to the output variable
+	    // This should probably be done in the Parser instead, as then we could
+	    // just attact normal signal attributes to it.
 	    if (AstFunc* funcp = nodep->castFunc()) {
 		if (!funcp->fvarp()->castVar()) {
 		    AstRange* rangep = funcp->fvarp()->castRange();
@@ -221,6 +230,7 @@ private:
 		    newvarp->isSigned(funcp->isSigned());
 		    newvarp->funcReturn(true);
 		    newvarp->trace(false);  // Not user visible
+		    newvarp->attrIsolateAssign(funcp->attrIsolateAssign());
 		    funcp->addFvarp(newvarp);
 		    // Explicit insert required, as the var name shadows the upper level's task name
 		    m_curVarsp->insert(newvarp->name(), newvarp);
@@ -362,7 +372,8 @@ private:
 	    }
 	}
 	// Deal with implicit definitions
-	if (m_idState==ID_RESOLVE && nodep->modVarp()) {
+	if (m_idState==ID_RESOLVE && nodep->modVarp()
+	    && !nodep->svImplicit()) {   // SV 19.11.3: .name pins don't allow implicit decls
 	    pinImplicitExprRecurse(nodep->exprp());
 	}
 	nodep->iterateChildren(*this);

src/V3LinkCells.cpp

@@ -163,6 +163,32 @@ private:
 		new V3GraphEdge(&m_graph, vertex(m_modp), vertex(modp), 1, false);
 	    }
 	}
+	// Convert .* to list of pins
+	if (nodep->modp() && nodep->pinStar()) {
+	    // Note what pins exist
+	    UINFO(9,"  CELL .* connect "<<nodep<<endl);
+	    V3SymTable  ports;		// Symbol table of all connected port names
+	    for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
+		if (pinp->name()=="") pinp->v3error("Connect by position is illegal in .* connected cells");
+		if (!ports.findIdName(pinp->name())) {
+		    ports.insert(pinp->name(), pinp);
+		}
+	    }
+	    // We search ports, rather then in/out declarations as they aren't resolved yet,
+	    // and it's easier to do it now then in V3Link when we'd need to repeat steps.
+	    for (AstNode* portnodep = nodep->modp()->stmtsp(); portnodep; portnodep=portnodep->nextp()) {
+		if (AstPort* portp = portnodep->castPort()) {
+		    if (!ports.findIdName(portp->name())) {
+			UINFO(9,"    need PORT  "<<portp<<endl);
+			// Create any not already connected
+			AstPin* newp = new AstPin(nodep->fileline(),0,portp->name(),
+						  new AstVarRef(nodep->fileline(),portp->name(),false));
+			newp->svImplicit(true);
+			nodep->addPinsp(newp);
+		    }
+		}
+	    }
+	}
 	// Convert unnamed pins to pin number based assignments
 	for (AstPin* pinp = nodep->pinsp(); pinp; pinp=pinp->nextp()->castPin()) {
 	    if (pinp->name()=="") pinp->name("__pinNumber"+cvtToStr(pinp->pinNum()));

src/V3LinkLevel.cpp

@@ -92,8 +92,8 @@ void V3LinkLevel::modSortByLevel() {
     AstModule* topp = NULL;
     for (AstModule* nodep = v3Global.rootp()->modulesp(); nodep; nodep=nodep->nextp()->castModule()) {
 	if (nodep->level()<=2) {
-	    if (topp) nodep->v3error("Unsupported: Multiple top level modules: "
-				     <<nodep->prettyName()<<" and "<<topp->prettyName());
+	    if (topp) nodep->v3warn(MULTITOP, "Unsupported: Multiple top level modules: "
+				    <<nodep->prettyName()<<" and "<<topp->prettyName());
 	    topp = nodep;
 	}
 	vec.push_back(nodep);

src/V3LinkParse.cpp

@@ -89,6 +89,10 @@ private:
 	// VarRef: Parse its reference
 	UINFO(5,"   "<<nodep<<endl);
 	// May be a varref inside a select, etc, so save state and recurse
+	string		oldText = m_dotText;
+	bool		oldDot = m_inModDot;
+	AstParseRefExp  oldExp = m_exp;
+	AstText*	oldBasep = m_baseTextp;
 	{
 	    // Replace the parsed item with its child IE the selection tree down to the varref itself
 	    // Do this before iterating, so we don't have to process the edited tree twice
@@ -117,8 +121,14 @@ private:
 	    } else {
 		nodep->v3fatalSrc("Unknown ParseRefExp type\n");
 	    }
+	    nodep->deleteTree(); nodep=NULL;
+	}
+	if (m_exp != AstParseRefExp::FUNC) {  // Fuctions need to look at the name themself
+	    m_dotText = oldText;
+	    m_inModDot = oldDot;
+	    m_exp = oldExp;
+	    m_baseTextp = oldBasep;
 	}
-	nodep->deleteTree(); nodep=NULL;
     }
     virtual void visit(AstDot* nodep, AstNUser*) {
 	UINFO(5,"     "<<nodep<<endl);

src/V3LinkResolve.cpp

@@ -54,6 +54,7 @@ private:
     // Below state needs to be preserved between each module call.
     AstModule*	m_modp;		// Current module
     AstNodeFTask* m_ftaskp;	// Function or task we're inside
+    AstVAssert*	m_assertp;	// Current assertion
 
     //int debug() { return 9; }
 
@@ -72,13 +73,23 @@ private:
 	nodep->iterateChildren(*this);
 	m_modp = NULL;
     }
+    virtual void visit(AstVAssert* nodep, AstNUser*) {
+	if (m_assertp) nodep->v3error("Assert not allowed under another assert");
+	m_assertp = nodep;
+	nodep->iterateChildren(*this);
+	m_assertp = NULL;
+    }
+
     virtual void visit(AstVar* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	if (nodep->arraysp() && nodep->isIO()) {
 	    nodep->v3error("Arrayed variables may not be inputs nor outputs");
 	}
 	if (m_ftaskp) nodep->funcLocal(true);
-	if (nodep->isSigPublic()) m_modp->modPublic(true);	// Avoid flattening if signals are exposed
+	if (nodep->isSigModPublic()) {
+	    nodep->sigModPublic(false);  // We're done with this attribute
+	    m_modp->modPublic(true);	// Avoid flattening if signals are exposed
+	}
     }
 
     virtual void visit(AstNodeVarRef* nodep, AstNUser*) {
@@ -317,6 +328,13 @@ private:
     virtual void visit(AstDisplay* nodep, AstNUser*) {
 	nodep->iterateChildren(*this);
 	if (nodep->filep()) expectDescriptor(nodep, nodep->filep()->castNodeVarRef());
+	if (!m_assertp
+	    && (nodep->displayType() == AstDisplayType::INFO
+		|| nodep->displayType() == AstDisplayType::WARNING
+		|| nodep->displayType() == AstDisplayType::ERROR
+		|| nodep->displayType() == AstDisplayType::FATAL)) {
+	    nodep->v3error(nodep->verilogKwd()+" only allowed under a assertion.");
+	}
     }
 
     virtual void visit(AstScCtor* nodep, AstNUser*) {
@@ -345,6 +363,7 @@ public:
     LinkResolveVisitor(AstNetlist* rootp) {
 	m_ftaskp = NULL;
 	m_modp = NULL;
+	m_assertp = NULL;
 	//
 	rootp->accept(*this);
     }

src/V3Number.cpp

@@ -296,6 +296,11 @@ V3Number& V3Number::setAllBitsZ() {
     for (int i=0; i<words(); i++) { m_value[i]=0; m_valueX[i] = ~0; }
     return *this;
 }
+V3Number& V3Number::setMask(int nbits) {
+    setZero();
+    for (int bit=0; bit<nbits; bit++) { setBit(bit,1); }
+    return *this;
+}
 
 //======================================================================
 // ACCESSORS

src/V3Number.h

@@ -108,6 +108,7 @@ public:
     // SETTERS
     V3Number& setAllBitsX();
     V3Number& setAllBitsZ();
+    V3Number& setMask(int nbits);  // IE if nbits=1, then 0b1, if 2->0b11, if 3->0b111 etc
 
     // ACCESSORS
     string ascii(bool prefixed=true, bool cleanVerilog=false) const;

src/V3Options.cpp

@@ -48,7 +48,8 @@ struct V3OptionsImp {
     list<string>	m_allArgs;	// List of every argument encountered
     list<string>	m_incDirs;	// Include directories (ordered)
     set<string>		m_incDirSet;	// Include directories (for removing duplicates)
-    set<string>		m_libExts;	// Library extensions
+    list<string>	m_libExts;	// Library extensions (ordered)
+    set<string>		m_libExtSet;	// Library extensions (for removing duplicates)
     DirMap		m_dirMap;	// Directory listing
 
     // ACCESSOR METHODS
@@ -59,8 +60,9 @@ struct V3OptionsImp {
 	}
     }
     void addLibExt(const string& libext) {
-	if (m_libExts.find(libext) == m_libExts.end()) {
-	    m_libExts.insert(libext);
+	if (m_libExtSet.find(libext) == m_libExtSet.end()) {
+	    m_libExtSet.insert(libext);
+	    m_libExts.push_back(libext);
 	}
     }
     V3OptionsImp() {}
@@ -193,7 +195,7 @@ string V3Options::filePath (FileLine* fl, const string& modname, const string& e
     // using the incdir and libext's.
     // Return "" if not found.
     for (list<string>::iterator dirIter=m_impp->m_incDirs.begin(); dirIter!=m_impp->m_incDirs.end(); ++dirIter) {
-	for (set<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
+	for (list<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
 	    string fn = filenameFromDirBase(*dirIter,modname+*extIter);
 	    string exists = fileExists(fn);
 	    if (exists!="") {
@@ -214,7 +216,7 @@ string V3Options::filePath (FileLine* fl, const string& modname, const string& e
 	} else {
 	    fl->v3error("Looked in:"<<endl);
 	    for (list<string>::iterator dirIter=m_impp->m_incDirs.begin(); dirIter!=m_impp->m_incDirs.end(); ++dirIter) {
-		for (set<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
+		for (list<string>::iterator extIter=m_impp->m_libExts.begin(); extIter!=m_impp->m_libExts.end(); ++extIter) {
 		    string fn = filenameFromDirBase(*dirIter,modname+*extIter);
 		    fl->v3error("      "<<fn<<endl);
 		}
@@ -353,6 +355,10 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift;
 		m_outputSplitCFuncs = atoi(argv[i]);
 	    }
+	    else if ( !strcmp (sw, "-trace-depth") ) {
+		shift;
+		m_traceDepth = atoi(argv[i]);
+	    }
 	    else if ( !strcmp (sw, "-unroll-count") ) { // Undocumented optimization tweak
 		shift;
 		m_unrollCount = atoi(argv[i]);
@@ -377,6 +383,7 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 	    else if ( onoff   (sw, "-ignc", flag/*ref*/) )	{ m_ignc = flag; }
 	    else if ( onoff   (sw, "-inhibit-sim", flag/*ref*/)){ m_inhibitSim = flag; }
 	    else if ( onoff   (sw, "-l2name", flag/*ref*/) )	{ m_l2Name = flag; }
+	    else if ( onoff   (sw, "-lint-only", flag/*ref*/) )	{ m_lintOnly = flag; }
 	    else if ( onoff   (sw, "-pins64", flag/*ref*/) )	{ m_pins64 = flag; }
 	    else if ( !strcmp (sw, "-private") )		{ m_public = false; }
 	    else if ( onoff   (sw, "-profile-cfuncs", flag/*ref*/) )	{ m_profileCFuncs = flag; }
@@ -447,18 +454,20 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		    V3Error::pretendError(code, true);
 		}
 	    }
-	    else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
-		shift;
-		if (!strcmp (argv[i], "0")) { m_xAssign="0"; }
-		else if (!strcmp (argv[i], "1")) { m_xAssign="1"; }
-		else if (!strcmp (argv[i], "unique")) { m_xAssign="unique"; }
-		else {
-		    fl->v3fatal("Unknown setting for -x-assign: "<<sw);
-		}
-	    }
 	    else if ( !strcmp (sw, "-bin") && (i+1)<argc ) {
 		shift; m_bin = argv[i];
 	    }
+	    else if ( !strcmp (sw, "-compiler") && (i+1)<argc) {
+		shift;
+		if (!strcmp (argv[i], "gcc")) {
+		    m_compLimitParens = 0;
+		} else if (!strcmp (argv[i], "msvc")) {
+		    m_compLimitParens = 80;   // 128, but allow some room
+		    m_compLimitBlocks = 80;   // 128, but allow some room
+		} else {
+		    fl->v3fatal("Unknown setting for --compiler: "<<argv[i]);
+		}
+	    }
 	    else if ( !strcmp (sw, "-f") && (i+1)<argc ) {
 		shift;
 		parseOptsFile(fl, argv[i]);
@@ -473,6 +482,15 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift; m_prefix = argv[i];
 		if (m_modPrefix=="") m_modPrefix = m_prefix;
 	    }
+	    else if ( !strcmp (sw, "-x-assign") && (i+1)<argc) {
+		shift;
+		if (!strcmp (argv[i], "0")) { m_xAssign="0"; }
+		else if (!strcmp (argv[i], "1")) { m_xAssign="1"; }
+		else if (!strcmp (argv[i], "unique")) { m_xAssign="unique"; }
+		else {
+		    fl->v3fatal("Unknown setting for --x-assign: "<<argv[i]);
+		}
+	    }
 	    else if ( !strcmp (sw, "-y")) {
 		shift; addIncDir (string (argv[i]));
 	    }
@@ -568,6 +586,7 @@ V3Options::V3Options() {
     m_exe = false;
     m_ignc = false;
     m_l2Name = true;
+    m_lintOnly = false;
     m_makeDepend = true;
     m_makePhony = false;
     m_outFormatOk = false;
@@ -587,9 +606,13 @@ V3Options::V3Options() {
     m_inlineMult = 2000;
     m_outputSplit = 0;
     m_outputSplitCFuncs = 0;
+    m_traceDepth = 0;
     m_unrollCount = 64;
     m_unrollStmts = 20;
 
+    m_compLimitParens = 0;
+    m_compLimitBlocks = 0;
+
     m_makeDir = "obj_dir";
     m_bin = "";
     m_flags = "";

src/V3Options.h

@@ -56,6 +56,7 @@ class V3Options {
     bool	m_ignc;		// main switch: --ignc
     bool	m_inhibitSim;	// main switch: --inhibit-sim
     bool	m_l2Name;	// main switch: --l2name
+    bool	m_lintOnly;	// main switch: --lint-only
     bool	m_outFormatOk;	// main switch: --cc, --sc or --sp was specified
     bool	m_pins64;	// main switch: --pins64
     bool	m_profileCFuncs;// main switch: --profile-cfuncs
@@ -72,9 +73,13 @@ class V3Options {
     int		m_inlineMult;	// main switch: --inline-mult
     int		m_outputSplit;	// main switch: --output-split
     int		m_outputSplitCFuncs;// main switch: --output-split-cfuncs
+    int		m_traceDepth;	// main switch: --trace-depth
     int		m_unrollCount;	// main switch: --unroll-count
     int		m_unrollStmts;	// main switch: --unroll-stmts
 
+    int		m_compLimitBlocks;	// compiler selection options
+    int		m_compLimitParens;	// compiler selection options
+
     string	m_bin;		// main switch: --bin {binary}
     string	m_flags;	// main switch: -f {name}
     string	m_top;		// main switch: Top .v file name
@@ -149,15 +154,20 @@ class V3Options {
     bool psl() const { return m_psl; }
     bool allPublic() const { return m_public; }
     bool l2Name() const { return m_l2Name; }
+    bool lintOnly() const { return m_lintOnly; }
     bool ignc() const { return m_ignc; }
     bool inhibitSim() const { return m_inhibitSim; }
 
     int	   inlineMult() const { return m_inlineMult; }
     int	   outputSplit() const { return m_outputSplit; }
     int	   outputSplitCFuncs() const { return m_outputSplitCFuncs; }
+    int	   traceDepth() const { return m_traceDepth; }
     int	   unrollCount() const { return m_unrollCount; }
     int	   unrollStmts() const { return m_unrollStmts; }
 
+    int    compLimitBlocks() const { return m_compLimitBlocks; }
+    int    compLimitParens() const { return m_compLimitParens; }
+
     string makeDir() const { return m_makeDir; }
     string prefix() const { return m_prefix; }
     string modPrefix() const { return m_modPrefix; }
@@ -165,6 +175,7 @@ class V3Options {
     const V3StringSet& cppFiles() const { return m_cppFiles; }
     const V3StringSet& libraryFiles() const { return m_libraryFiles; }
 
+
     // ACCESSORS (optimization options)
     bool oAcycSimp() const { return m_oAcycSimp; }
     bool oCase() const { return m_oCase; }

src/V3Order.cpp

@@ -382,6 +382,14 @@ private:
 	    //nodep->v3warn(GENCLK,"Signal unoptimizable: Generated clock: "<<nodep->prettyName());
 	} else if (nodep->varp()->isSigPublic()) {
 	    nodep->v3warn(UNOPT,"Signal unoptimizable: Feedback to public clock or circular logic: "<<nodep->prettyName());
+	    if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPT)) {
+		nodep->fileline()->warnOff(V3ErrorCode::UNOPT, true);  // Complain just once
+		// Give the user an example.
+		bool tempWeight = (edgep && edgep->weight()==0);
+		if (tempWeight) edgep->weight(1);  // Else the below loop detect can't see the loop
+		m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
+		if (tempWeight) edgep->weight(0);
+	    }
 	} else {
 	    // We don't use UNOPT, as there are lots of V2 places where it was needed, that aren't any more
 	    // First v3warn not inside warnIsOff so we can see the suppressions with --debug

src/V3PreProc.cpp

@@ -301,12 +301,12 @@ void V3PreProcImp::comment(const string& text) {
 	    if (commentTokenMatch(cmd/*ref*/, "parallel_case")) {
 		insertUnreadback ("/*verilator parallel_case*/");
 	    }
-	    if (commentTokenMatch(cmd/*ref*/, "one_hot")) {
-		insertUnreadback ("/*verilator one_hot*/ "+cmd+";");
-	    }
-	    if (commentTokenMatch(cmd/*ref*/, "one_cold")) {
-		insertUnreadback ("/*verilator one_cold*/ "+cmd+";");
-	    }
+	    //if (commentTokenMatch(cmd/*ref*/, "one_hot")) {
+	    //	insertUnreadback ("/*verilator one_hot*/ "+cmd+";");
+	    //}
+	    //if (commentTokenMatch(cmd/*ref*/, "one_cold")) {
+	    //	insertUnreadback ("/*verilator one_cold*/ "+cmd+";");
+	    //}
 	    // else ignore the comment we don't recognize
 	} // else no assertions
     } else {

src/V3Premit.cpp

@@ -71,14 +71,18 @@ private:
 	//   ASSIGN(CONST*here*, VARREF(!sc))
 	//   ARRAYSEL(*here*, ...)   (No wides can be in any argument but first, so we don't check which arg is wide)
 	//   ASSIGN(x, SEL*HERE*(ARRAYSEL()...)   (m_assignLhs==true handles this.)
+	//UINFO(9, "   Check: "<<nodep<<endl);
+	//UINFO(9, "     Detail stmtp="<<(m_stmtp?"Y":"N")<<" U="<<(nodep->user()?"Y":"N")<<" IW "<<(nodep->isWide()?"Y":"N")<<endl);
 	if (m_stmtp
 	    && !nodep->user()) {	// Not already done
 	    if (nodep->isWide()) {		// Else might be cell interconnect or something
 		if (m_assignLhs) {
-		} else if (nodep->backp()->castNodeAssign()
-			   && assignNoTemp(nodep->backp()->castNodeAssign())) {
+		} else if (nodep->firstAbovep()
+			   && nodep->firstAbovep()->castNodeAssign()
+			   && assignNoTemp(nodep->firstAbovep()->castNodeAssign())) {
 		    // Not much point if it's just a direct assignment to a constant
-		} else if (nodep->backp()->castArraySel()) {  // ArraySel's are pointer refs, ignore
+		} else if (nodep->firstAbovep()
+			   && nodep->firstAbovep()->castArraySel()) {  // ArraySel's are pointer refs, ignore
 		} else {
 		    UINFO(4,"Cre Temp: "<<nodep<<endl);
 		    createDeepTemp(nodep);
@@ -140,6 +144,7 @@ private:
     virtual void visit(AstCFunc* nodep, AstNUser*) {
 	m_funcp = nodep;
 	nodep->iterateChildren(*this);
+	m_funcp = NULL;
     }
     void startStatement(AstNode* nodep) {
 	m_assignLhs = false;

src/V3Read.cpp

@@ -62,10 +62,10 @@ public:
     // METHODS
     void stateExitPsl() {
 	if (YY_START != PSL) yyerror("Internal error: Exiting PSL state when not in PSL state");
-	BEGIN VLG;
+	yy_pop_state();
     }
     void statePushVlg() {
-	yy_push_state(VLG);
+	yy_push_state(STATE_VERILOG_RECENT);
     }
     void statePop() {
 	yy_pop_state();

src/V3Read.h

@@ -39,8 +39,11 @@ class V3Read {
     static V3Read*	s_readp;	// Current THIS, bison() isn't class based
     FileLine*	m_fileline;	// Filename/linenumber currently active
     bool	m_inLibrary;	// Currently reading a library vs. regular file
+    int		m_inBeginKwd;		// Inside a `begin_keywords
+    int		m_lastVerilogState;	// Last LEX state in `begin_keywords
     deque<string*> m_stringps;		// Created strings for later cleanup
     deque<V3Number*> m_numberps;	// Created numbers for later cleanup
+    deque<FileLine>  m_lintState;	// Current lint state for save/restore
     //int debug() { return 9; }
 
 protected:
@@ -53,7 +56,12 @@ protected:
     static void ppline (const char* text);
     static void incLineno() { s_readp->fileline()->incLineno(); }
     static void verilatorCmtLint(const char* text, bool on);
+    static void verilatorCmtLintSave();
+    static void verilatorCmtLintRestore();
     static void verilatorCmtBad(const char* text);
+    static void pushBeginKeywords(int state) { s_readp->m_inBeginKwd++; s_readp->m_lastVerilogState=state; }
+    static bool popBeginKeywords() { if (s_readp->m_inBeginKwd) { s_readp->m_inBeginKwd--; return true; } else return false; }
+    static int lastVerilogState() { return s_readp->m_lastVerilogState; }
 
 public: // But for internal use only
     static string* newString(const string& text) {
@@ -88,12 +96,15 @@ public: // But for internal use only
     static void stateExitPsl();	// Parser -> lexer communication
     static void statePushVlg();	// Parser -> lexer communication
     static void statePop();	// Parser -> lexer communication
+    static int stateVerilogRecent();	// Parser -> lexer communication
 
 public:
     // CREATORS
     V3Read(AstNetlist* rootp) {
 	m_rootp = rootp; m_lexerp = NULL;
 	m_inLibrary = false;
+	m_inBeginKwd = 0;
+	m_lastVerilogState = stateVerilogRecent();
     }
     ~V3Read() {
 	for (deque<string*>::iterator it = m_stringps.begin(); it != m_stringps.end(); ++it) {

src/V3Split.cpp

@@ -428,7 +428,7 @@ private:
 	AstNode* firstp = nodep;   // We may reorder, and nodep is no longer first.
 	void* oldBlockUser3 = nodep->user3p();   // May be overloaded in below loop, save it
 	nodep->user3p(NULL);
-	if (nodep->backp()->nextp()==nodep) nodep->v3fatalSrc("Node passed is in next list; should have processed all list at oncen");
+	if (!nodep->firstAbovep()) nodep->v3fatalSrc("Node passed is in next list; should have processed all list at once");
 	// Process it
 	if (!nodep->nextp()) {
 	    // Just one, so can't reorder.  Just look for more blocks/statements.

src/V3SplitAs.cpp

@@ -20,7 +20,7 @@
 //*************************************************************************
 // V3SplitAs's Transformations:
 //
-//	Search each ALWAYS for a VARREF lvalue with a /*isolate_asignments*/ attribute
+//	Search each ALWAYS for a VARREF lvalue with a /*isolate_assignments*/ attribute
 //	If found, color statements with both, assignment to that varref, or other assignments.
 //	Replicate the Always, and remove mis-colored duplicate code.
 //
@@ -166,12 +166,23 @@ private:
     virtual void visit(AstAlways* nodep, AstNUser*) {
 	// Are there any lvalue references below this?
 	// There could be more then one.  So, we process the first one found first.
-	if (!nodep->user()) {
+	AstVarScope* lastSplitVscp = NULL;
+	while (!nodep->user()) {
+	    // Find any splittable variables
 	    SplitAsFindVisitor visitor (nodep);
 	    m_splitVscp = visitor.splitVscp();
+	    if (m_splitVscp && m_splitVscp == lastSplitVscp) {
+		// We did this last time!  Something's stuck!
+		nodep->v3fatalSrc("Infinite loop in isolate_assignments removal for: "<<m_splitVscp->prettyName())
+		m_splitVscp = NULL;
+	    }
+	    lastSplitVscp = m_splitVscp;
+	    // Now isolate the always
 	    if (m_splitVscp) {
 		splitAlways(nodep);
 		m_statSplits++;
+	    } else {
+		nodep->user(true);
 	    }
 	}
     }

src/V3Stats.cpp

@@ -63,9 +63,8 @@ private:
 	m_instrs += nodep->instrCount();
 	if (m_counting) {
 	    ++m_statTypeCount[nodep->type()];
-	    if (nodep->backp() && nodep->backp()->nextp()!=nodep) {
-		// Grab only those above, not those "back"
-		++m_statAbove[nodep->backp()->type()][nodep->type()];
+	    if (nodep->firstAbovep()) { // Grab only those above, not those "back"
+		++m_statAbove[nodep->firstAbovep()->type()][nodep->type()];
 	    }
 	    m_statInstr += nodep->instrCount();
 	    if (m_cfuncp && !m_cfuncp->slow()) m_statInstrFast += nodep->instrCount();

src/V3Task.cpp

@@ -306,6 +306,7 @@ private:
 	AstVar* newvarp = new AstVar (invarp->fileline(), AstVarType::BLOCKTEMP,
 				      name, invarp);
 	newvarp->funcLocal(false);
+	newvarp->propagateAttrFrom(invarp);
 	m_modp->addStmtp(newvarp);
 	AstVarScope* newvscp = new AstVarScope (newvarp->fileline(), m_scopep, newvarp);
 	m_scopep->addVarp(newvscp);
@@ -628,7 +629,7 @@ private:
 	if (!funcp) nodep->v3fatalSrc("unlinked");
 	// Inline func refs in the function
 	iterateIntoFTask(funcp);
-	// Create output variabls
+	// Create output variable
 	string namePrefix = "__Vfunc_"+funcp->shortName()+"__"+cvtToStr(m_modNCalls++);
 	AstVarScope* outvscp = createVarScope (funcp->fvarp()->castVar(),
 					       namePrefix+"__out");

src/V3Unroll.cpp

@@ -252,7 +252,12 @@ private:
 			if (clonedIncsp) {
 			    // Previous iteration of loop set the variable.
 			    // This set is redundant with this next iteration and can be removed.
-			    clonedIncsp->unlinkFrBack()->deleteTree();
+			    if (clonedIncsp == newbodysp) {  // Increment was only thing in list
+				newbodysp = NULL;
+			    } else {
+				clonedIncsp->unlinkFrBack();
+			    }
+			    clonedIncsp->deleteTree();
 			}
 			clonedIncsp = incp->clonep(); if (!clonedIncsp) nodep->v3fatalSrc("inc failed");
 		    }

src/V3Width.cpp

@@ -575,6 +575,13 @@ private:
 	nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
 	widthCheckReduce(nodep,"Property",nodep->propp(),1,1);	// it's like a if() condition.
     }
+    virtual void visit(AstVAssert* nodep, AstNUser*) {
+	// TOP LEVEL NODE
+	nodep->propp()->iterateAndNext(*this,WidthVP(1,1,BOTH).p());
+	nodep->passsp()->iterateAndNext(*this);
+	nodep->failsp()->iterateAndNext(*this);
+	widthCheckReduce(nodep,"Property",nodep->propp(),1,1);	// it's like a if() condition.
+    }
     virtual void visit(AstPin* nodep, AstNUser*) {
 	//if (debug()) nodep->dumpTree(cout,"-  PinPre: ");
 	// TOP LEVEL NODE

src/Verilator.cpp

@@ -41,6 +41,7 @@
 #include "V3Dead.h"
 #include "V3Delayed.h"
 #include "V3Depth.h"
+#include "V3DepthBlock.h"
 #include "V3Descope.h"
 #include "V3EmitC.h"
 #include "V3EmitMk.h"
@@ -159,13 +160,11 @@ void process () {
 
     // Assertion insertion
     //    After we've added block coverage, but before other nasty transforms
-    if (v3Global.opt.assertOn() || v3Global.opt.psl()) {
-	V3AssertPre::assertPreAll(v3Global.rootp());
-	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assertpre.tree"));
-	//
-	V3Assert::assertAll(v3Global.rootp());
-	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assert.tree"));
-    }
+    V3AssertPre::assertPreAll(v3Global.rootp());
+    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assertpre.tree"));
+    //
+    V3Assert::assertAll(v3Global.rootp());
+    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("assert.tree"));
 
     // Add top level wrapper with instance pointing to old top
     // Must do this after we know the width of any parameters
@@ -381,6 +380,12 @@ void process () {
 
     //--MODULE OPTIMIZATIONS--------------
 
+    // Split deep blocks to appease MSVC++.  Must be before Localize.
+    if (!v3Global.opt.lintOnly() && v3Global.opt.compLimitBlocks()) {
+	V3DepthBlock::depthBlockAll(v3Global.rootp());
+	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("deepblock.tree"));
+    }
+
     // Move BLOCKTEMPS from class to local variables
     if (v3Global.opt.oLocalize()) {
 	V3Localize::localizeAll(v3Global.rootp());
@@ -435,24 +440,28 @@ void process () {
 	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("dead.tree"));
     }
 
-    // Fix very deep expressions
-    // Mark evaluation functions as member functions, if needed.
-    V3Depth::depthAll(v3Global.rootp());
-    //v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
+    if (!v3Global.opt.lintOnly()) {
+	// Fix very deep expressions
+	// Mark evaluation functions as member functions, if needed.
+	V3Depth::depthAll(v3Global.rootp());
+	//v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("depth.tree"));
 
-    // Branch prediction
-    V3Branch::branchAll(v3Global.rootp());
+	// Branch prediction
+	V3Branch::branchAll(v3Global.rootp());
 
-    // Add C casts when longs need to become long-long and vice-versa
-    // Note depth may insert something needing a cast, so this must be last.
-    V3Cast::castAll(v3Global.rootp());
-    v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));
+	// Add C casts when longs need to become long-long and vice-versa
+	// Note depth may insert something needing a cast, so this must be last.
+	V3Cast::castAll(v3Global.rootp());
+	v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("cast.tree"));	
+    }
 
     V3Error::abortIfErrors();
 
     // Output the text
-    V3EmitC::emitcSyms();
-    V3EmitC::emitcTrace();
+    if (!v3Global.opt.lintOnly()) {
+	V3EmitC::emitcSyms();
+	V3EmitC::emitcTrace();
+    }
     V3EmitC::emitc();
 
     // Statistics
@@ -461,8 +470,10 @@ void process () {
 	V3Stats::statsReport();
     }
 
-    // Makefile must be after all other emitters
-    V3EmitMk::emitmk(v3Global.rootp());
+    if (!v3Global.opt.lintOnly()) {
+	// Makefile must be after all other emitters
+	V3EmitMk::emitmk(v3Global.rootp());
+    }
 }
 
 //######################################################################
@@ -483,11 +494,11 @@ int main(int argc, char** argv, char** env) {
     v3Global.opt.bin(argv[0]);
     string argString = V3Options::argString(argc-1, argv+1);
     v3Global.opt.parseOpts(new FileLine("COMMAND_LINE",0), argc-1, argv+1);
-    if (v3Global.opt.coverage() && !v3Global.opt.systemPerl()) {
+    if (v3Global.opt.coverage() && !v3Global.opt.systemPerl() && !v3Global.opt.lintOnly()) {
 	v3fatal("Unsupported: Coverage analysis requires --sp output.");
     }
-    if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly()) {
-	v3fatal("verilator: Need --cc, --sc, --sp or --E option");
+    if (!v3Global.opt.outFormatOk() && !v3Global.opt.preprocOnly() && !v3Global.opt.lintOnly()) {
+	v3fatal("verilator: Need --cc, --sc, --sp, --lint-only or --E option");
     }
 
     V3Error::abortIfErrors();
@@ -496,6 +507,7 @@ int main(int argc, char** argv, char** env) {
     V3File::addSrcDepend(v3Global.opt.bin());
     if (v3Global.opt.skipIdentical()
 	&& !v3Global.opt.preprocOnly()
+	&& !v3Global.opt.lintOnly()
 	&& V3File::checkTimes(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__verFiles.dat", argString)) {
 	UINFO(1,"--skip-identical: No change to any source files, exiting\n");
 	exit(0);
@@ -528,10 +540,11 @@ int main(int argc, char** argv, char** env) {
     v3Global.rootp()->dumpTreeFile(v3Global.debugFilename("final.tree",99));
     V3Error::abortIfErrors();
 
-    if (v3Global.opt.makeDepend()) {
+    if (!v3Global.opt.lintOnly() && v3Global.opt.makeDepend()) {
 	V3File::writeDepend(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__ver.d");
     }
-    if (v3Global.opt.skipIdentical() || v3Global.opt.makeDepend()) { 
+    if (!v3Global.opt.lintOnly()
+	&& (v3Global.opt.skipIdentical() || v3Global.opt.makeDepend())) { 
 	V3File::writeTimes(v3Global.opt.makeDir()+"/"+v3Global.opt.prefix()+"__verFiles.dat", argString);
     }
 

src/config_build.h.in

@@ -24,7 +24,7 @@
 //**********************************************************************
 //**** Version and host name
 
-#define DTVERSION	"Verilator 3.632 1/17/2007"
+#define DTVERSION	"Verilator 3.650 4/20/2007"
 
 //**********************************************************************
 //**** Functions

src/verilog.y

@@ -53,6 +53,7 @@ public:
     static AstCase*	s_caseAttrp;	// Current case statement for attribute adding
     static AstRange*	s_varRangep;	// Pointer to range for next signal declaration
     static int		s_pinNum;	// Pin number currently parsing
+    static bool		s_pinStar;	// Encountered SystemVerilog .*
     static string	s_instModule;	// Name of module referenced for instantiations
     static AstPin*	s_instParamp;	// Parameters for instantiations
     static bool		s_trace;	// Tracing is turned on
@@ -60,6 +61,11 @@ public:
     static AstVar*  createVariable(FileLine* fileline, string name, AstRange* arrayp);
     static AstNode* createSupplyExpr(FileLine* fileline, string name, int value);
     static AstText* createTextQuoted(FileLine* fileline, string text);
+    static AstDisplay* createDisplayError(FileLine* fileline) {
+	AstDisplay* nodep = new AstDisplay(fileline,AstDisplayType::ERROR,  "", NULL,NULL);
+	nodep->addNext(new AstStop(fileline)); 
+	return nodep;
+    }
     static string   deQuote(FileLine* fileline, string text);
 };
 
@@ -70,6 +76,7 @@ AstVarType	V3Parse::s_varIO = AstVarType::UNKNOWN;
 bool		V3Parse::s_varSigned = false;
 AstRange*	V3Parse::s_varRangep = NULL;
 int 		V3Parse::s_pinNum = -1;
+bool		V3Parse::s_pinStar = false;
 string		V3Parse::s_instModule;
 AstPin*		V3Parse::s_instParamp = NULL;
 AstVar*		V3Parse::s_varAttrp = NULL;
@@ -103,7 +110,9 @@ class AstSenTree;
     AstBegin*	beginp;
     AstCase*	casep;
     AstCaseItem* caseitemp;
+    AstCell*	cellp;
     AstConst*	constp;
+    AstFunc*	funcp;
     AstFuncRef*	funcrefp;
     AstModule*	modulep;
     AstPin*	pinp;
@@ -134,20 +143,27 @@ class AstSenTree;
 %token<fileline>	yASSERT		"assert"
 %token<fileline>	yCLOCK		"clock"
 %token<fileline>	yCOVER		"cover"
+%token<fileline>	yDO		"do"
 %token<fileline>	yFINAL		"final"
 %token<fileline>	yPSL		"psl"
 %token<fileline>	yREPORT		"report"
 %token<fileline>	yTRUE		"true"
+%token<fileline>	yWHILE		"while"
+
+%token<fileline>	yPSL_ASSERT	"PSL assert"
 
 %token<fileline>	yD_BITS		"$bits"
 %token<fileline>	yD_C		"$c"
 %token<fileline>	yD_COUNTONES	"$countones"
 %token<fileline>	yD_DISPLAY	"$display"
+%token<fileline>	yD_ERROR	"$error"
+%token<fileline>	yD_FATAL	"$fatal"
 %token<fileline>	yD_FCLOSE	"$fclose"
 %token<fileline>	yD_FDISPLAY	"$fdisplay"
 %token<fileline>	yD_FINISH	"$finish"
 %token<fileline>	yD_FOPEN	"$fopen"
 %token<fileline>	yD_FWRITE	"$fwrite"
+%token<fileline>	yD_INFO		"$info"
 %token<fileline>	yD_ISUNKNOWN	"$isunknown"
 %token<fileline>	yD_ONEHOT	"$onehot"
 %token<fileline>	yD_ONEHOT0	"$onehot0"
@@ -157,6 +173,7 @@ class AstSenTree;
 %token<fileline>	yD_STOP		"$stop"
 %token<fileline>	yD_TIME		"$time"
 %token<fileline>	yD_UNSIGNED	"$unsigned"
+%token<fileline>	yD_WARNING	"$warning"
 %token<fileline>	yD_WRITE	"$write"
 
 %token<fileline>	yVL_CLOCK		"/*verilator sc_clock*/"
@@ -168,6 +185,7 @@ class AstSenTree;
 %token<fileline>	yVL_NO_INLINE_TASK	"/*verilator no_inline_task*/"
 %token<fileline>	yVL_PARALLEL_CASE	"/*verilator parallel_case*/"
 %token<fileline>	yVL_PUBLIC		"/*verilator public*/"
+%token<fileline>	yVL_PUBLIC_FLAT		"/*verilator public_flat*/"
 %token<fileline>	yVL_PUBLIC_MODULE	"/*verilator public_module*/"
 %token<fileline>	yVL_ISOLATE_ASSIGNMENTS	"/*verilator isolate_assignments*/"
 %token<fileline>	yVL_TRACING_OFF		"/*verilator tracing_off*/"
@@ -225,12 +243,14 @@ class AstSenTree;
 %type<varp>	netSig netSigList
 %type<rangep>	rangeListE regrangeE anyrange rangeList delayrange portrangeE
 %type<varp>	param paramList
-%type<nodep>	instnameList instname
+%type<nodep>	instnameList
+%type<cellp>	instname
 %type<pinp>	cellpinList cellpinlist2 cellpinitemE instparamListE
 %type<nodep>	defpList defpOne
 %type<sentreep>	sensitivityE
 %type<senitemp>	senList senitem senitemEdge
-%type<nodep>	stmtBlock stmtList stmt stateCaseForIf
+%type<nodep>	stmtBlock stmtList stmt labeledStmt stateCaseForIf
+%type<nodep>	assertStmt
 %type<beginp>	beginNamed
 %type<casep>	caseStmt
 %type<caseitemp> caseList
@@ -246,13 +266,16 @@ class AstSenTree;
 %type<nodep>	idDotted
 %type<nodep>	strAsInt strAsText concIdList
 %type<nodep>	taskDecl
-%type<nodep>	varDeclList funcDecl funcVarList funcVar
+%type<nodep>	varDeclList
+%type<funcp>	funcDecl
+%type<nodep>	funcBody funcVarList funcVar
 %type<rangep>	funcRange
 %type<nodep>	gateDecl
 %type<nodep>	gateBufList gateNotList gateAndList gateNandList
 %type<nodep>	gateOrList gateNorList gateXorList gateXnorList
 %type<assignwp>	gateBuf gateNot gateAnd gateNand gateOr gateNor gateXor gateXnor
 %type<nodep>	gateAndPinList gateOrPinList gateXorPinList
+%type<nodep>	commaEListE
 
 %type<nodep>	pslStmt pslDir pslDirOne pslProp
 %type<nodep>	pslDecl
@@ -519,7 +542,8 @@ sigAttrList:	sigAttr					{}
 
 sigAttr:	yVL_CLOCK				{ V3Parse::s_varAttrp->attrScClocked(true); }
 	|	yVL_CLOCK_ENABLE			{ V3Parse::s_varAttrp->attrClockEn(true); }
-	|	yVL_PUBLIC				{ V3Parse::s_varAttrp->sigPublic(true); }
+	|	yVL_PUBLIC				{ V3Parse::s_varAttrp->sigPublic(true); V3Parse::s_varAttrp->sigModPublic(true); }
+	|	yVL_PUBLIC_FLAT				{ V3Parse::s_varAttrp->sigPublic(true); }
 	|	yVL_ISOLATE_ASSIGNMENTS			{ V3Parse::s_varAttrp->attrIsolateAssign(true); }
 	;
 
@@ -594,10 +618,10 @@ instnameList:	instname				{ $$ = $1; }
 	|	instnameList ',' instname		{ $$ = $1->addNext($3); }
 	;
 
-instname:	yID funcRange '(' cellpinList ')'	{ $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); }
+instname:	yID funcRange '(' cellpinList ')'	{ $$ = new AstCell($3,*$1,V3Parse::s_instModule,$4,V3Parse::s_instParamp,$2); $$->pinStar(V3Parse::s_pinStar); }
 	;
 
-cellpinList:	{V3Parse::s_pinNum=1;} cellpinlist2	{ $$ = $2; }
+cellpinList:	{V3Parse::s_pinNum=1; V3Parse::s_pinStar=false; } cellpinlist2	{ $$ = $2; }
 	;
 
 cellpinlist2:	cellpinitemE				{ $$ = $1; }
@@ -605,6 +629,8 @@ cellpinlist2:	cellpinitemE				{ $$ = $1; }
 	;
 
 cellpinitemE:	/* empty */				{ $$ = NULL; V3Parse::s_pinNum++; }
+	|	'.' '*'					{ $$ = NULL; if (V3Parse::s_pinStar) $1->v3error("Duplicate .* in a cell"); V3Parse::s_pinStar=true; }
+	|	'.' yID					{ $$ = new AstPin($1,V3Parse::s_pinNum++,*$2,new AstVarRef($1,*$2,false)); $$->svImplicit(true);}
 	|	'.' yID '(' ')'				{ $$ = NULL; V3Parse::s_pinNum++; }
 	|	'.' yID '(' expr ')'			{ $$ = new AstPin($1,V3Parse::s_pinNum++,*$2,$4); }
 	|	expr					{ $$ = new AstPin(CRELINE(),V3Parse::s_pinNum++,"",$1); }
@@ -647,6 +673,9 @@ stmtList:	stmtBlock				{ $$ = $1; }
 	;
 
 stmt:		';'					{ $$ = NULL; }
+	|	labeledStmt				{ $$ = $1; }
+	|	yID ':' labeledStmt			{ $$ = new AstBegin($2, *$1, $3); }  /*S05 block creation rule*/
+
 	|	varRefDotBit yLTE delayE expr ';'	{ $$ = new AstAssignDly($2,$1,$4); }
 	|	varRefDotBit '=' delayE expr ';'	{ $$ = new AstAssign($2,$1,$4); }
 	|	varRefDotBit '=' yD_FOPEN '(' expr ',' expr ')' ';'	{ $$ = new AstFOpen($3,$1,$5,$7); }
@@ -661,21 +690,31 @@ stmt:		';'					{ $$ = NULL; }
 	|	stateCaseForIf				{ $$ = $1; }
 	|	taskRef ';' 				{ $$ = $1; }
 
-	|	yD_DISPLAY  ';'					{ $$ = new AstDisplay($1,'\n',"",NULL,NULL); }
-	|	yD_DISPLAY  '(' ySTRING ')' ';'			{ $$ = new AstDisplay($1,'\n',*$3,NULL,NULL); }
-	|	yD_DISPLAY  '(' ySTRING ',' eList ')' ';'	{ $$ = new AstDisplay($1,'\n',*$3,NULL,$5); }
-	|	yD_WRITE    '(' ySTRING ')' ';'			{ $$ = new AstDisplay($1,'\0',*$3,NULL,NULL); }
-	|	yD_WRITE    '(' ySTRING ',' eList ')' ';' 	{ $$ = new AstDisplay($1,'\0',*$3,NULL,$5); }
-	|	yD_FDISPLAY '(' varRefDotBit ',' ySTRING ')' ';'		{ $$ = new AstDisplay($1,'\n',*$5,$3,NULL); }
-	|	yD_FDISPLAY '(' varRefDotBit ',' ySTRING ',' eList ')' ';' 	{ $$ = new AstDisplay($1,'\n',*$5,$3,$7); }
-	|	yD_FWRITE   '(' varRefDotBit ',' ySTRING ')' ';'		{ $$ = new AstDisplay($1,'\0',*$5,$3,NULL); }
-	|	yD_FWRITE   '(' varRefDotBit ',' ySTRING ',' eList ')' ';'	{ $$ = new AstDisplay($1,'\0',*$5,$3,$7); }
+	|	yD_DISPLAY  ';'							{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,"", NULL,NULL); }
+	|	yD_DISPLAY  '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$3,NULL,$4); }
+	|	yD_WRITE    '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::WRITE,  *$3,NULL,$4); }
+	|	yD_FDISPLAY '(' varRefDotBit ',' ySTRING commaEListE ')' ';' 	{ $$ = new AstDisplay($1,AstDisplayType::DISPLAY,*$5,$3,$6); }
+	|	yD_FWRITE   '(' varRefDotBit ',' ySTRING commaEListE ')' ';'	{ $$ = new AstDisplay($1,AstDisplayType::WRITE,  *$5,$3,$6); }
+	|	yD_INFO	    ';'							{ $$ = new AstDisplay($1,AstDisplayType::INFO,   "", NULL,NULL); }
+	|	yD_INFO	    '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::INFO,   *$3,NULL,$4); }
+	|	yD_WARNING  ';'							{ $$ = new AstDisplay($1,AstDisplayType::WARNING,"", NULL,NULL); }
+	|	yD_WARNING  '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::WARNING,*$3,NULL,$4); }
+	|	yD_ERROR    ';'							{ $$ = V3Parse::createDisplayError($1); }
+	|	yD_ERROR    '(' ySTRING commaEListE ')' ';'			{ $$ = new AstDisplay($1,AstDisplayType::ERROR,  *$3,NULL,$4);   $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    ';'							{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    '(' expr ')' ';'					{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  "", NULL,NULL); $$->addNext(new AstStop($1)); }
+	|	yD_FATAL    '(' expr ',' ySTRING commaEListE ')' ';'		{ $$ = new AstDisplay($1,AstDisplayType::FATAL,  *$5,NULL,$6);   $$->addNext(new AstStop($1)); }
+
 	|	yD_READMEMB '(' expr ',' varRefMem ')' ';'			{ $$ = new AstReadMem($1,false,$3,$5,NULL,NULL); }
 	|	yD_READMEMB '(' expr ',' varRefMem ',' expr ')' ';'		{ $$ = new AstReadMem($1,false,$3,$5,$7,NULL); }
 	|	yD_READMEMB '(' expr ',' varRefMem ',' expr ',' expr ')' ';'	{ $$ = new AstReadMem($1,false,$3,$5,$7,$9); }
 	|	yD_READMEMH '(' expr ',' varRefMem ')' ';'			{ $$ = new AstReadMem($1,true, $3,$5,NULL,NULL); }
 	|	yD_READMEMH '(' expr ',' varRefMem ',' expr ')' ';'		{ $$ = new AstReadMem($1,true, $3,$5,$7,NULL); }
 	|	yD_READMEMH '(' expr ',' varRefMem ',' expr ',' expr ')' ';'	{ $$ = new AstReadMem($1,true, $3,$5,$7,$9); }
+
+	;
+
+labeledStmt:	assertStmt				{ $$ = $1; }
 	;
 
 stateCaseForIf: caseStmt caseAttrE caseList yENDCASE	{ $$ = $1; $1->addItemsp($3); }
@@ -685,6 +724,13 @@ stateCaseForIf: caseStmt caseAttrE caseList yENDCASE	{ $$ = $1; $1->addItemsp($3
 							{ $$ = new AstFor($1, new AstAssign($4,$3,$5)
 									  ,$7, new AstAssign($10,$9,$11)
 									  ,$13);}
+	|	yWHILE '(' expr ')' stmtBlock		{ $$ = new AstWhile($1,$3,$5);}
+	|	yDO stmtBlock yWHILE '(' expr ')'	{ $$ = $2->cloneTree(true); $$->addNext(new AstWhile($1,$5,$2));}
+	;
+
+assertStmt:	yASSERT '(' expr ')' stmtBlock %prec yLOWER_THAN_ELSE	{ $$ = new AstVAssert($1,$3,$5, V3Parse::createDisplayError($1)); }
+	|	yASSERT '(' expr ')'           yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,NULL,$6); }
+	|	yASSERT '(' expr ')' stmtBlock yELSE stmtBlock		{ $$ = new AstVAssert($1,$3,$5,$7);   }
 	;
 
 caseStmt: 	yCASE  '(' expr ')' 			{ $$ = V3Parse::s_caseAttrp = new AstCase($1,false,$3,NULL); }
@@ -713,8 +759,13 @@ taskDecl: 	yTASK yID ';'             stmtBlock yENDTASK	{ $$ = new AstTask ($1,*
 	| 	yTASK yID ';' funcVarList stmtBlock yENDTASK	{ $$ = new AstTask ($1,*$2,$4); $4->addNextNull($5); }
 	;
 
-funcDecl: 	yFUNCTION         funcRange yID ';' funcVarList stmtBlock yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); $5->addNextNull($6);}
-	|	yFUNCTION ySIGNED funcRange yID ';' funcVarList stmtBlock yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $6->addNextNull($7); $$->isSigned(true); }
+funcDecl: 	yFUNCTION         funcRange yID				';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$5,$2); }
+	|	yFUNCTION ySIGNED funcRange yID				';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$6,$3); $$->isSigned(true); }
+	| 	yFUNCTION         funcRange yID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$3,$6,$2); $$->attrIsolateAssign(true);}
+	|	yFUNCTION ySIGNED funcRange yID yVL_ISOLATE_ASSIGNMENTS ';' funcBody yENDFUNCTION { $$ = new AstFunc ($1,*$4,$7,$3); $$->attrIsolateAssign(true); $$->isSigned(true); }
+	;
+
+funcBody:	funcVarList stmtBlock			{ $$ = $1;$1->addNextNull($2); }
 	;
 
 funcRange:	'[' constExpr ':' constExpr ']'		{ $$ = new AstRange($1,$2,$4); }
@@ -824,6 +875,11 @@ eList:		expr					{ $$ = $1; }
 	|	eList ',' expr				{ $$ = $1;$1->addNext($3); }
 	;
 
+commaEListE:	/* empty */				{ $$ = NULL; }
+	|	',' eList				{ $$ = $2; }
+	;
+
+
 // Gate declarations
 gateDecl: 	yBUF  gateBufList ';'			{ $$ = $2; }
 	|	yNOT  gateNotList ';'			{ $$ = $2; }
@@ -1003,8 +1059,8 @@ pslDir:		yID ':' pslDirOne			{ $$ = $3; }  // ADD: Create label on $1
 	;
 
 //ADD:	|	yRESTRICT pslSequence ';'		{ $$ = PSLUNSUP(new AstPslRestrict($1,$2)); }
-pslDirOne:	yASSERT pslProp ';'			{ $$ = new AstPslAssert($1,$2); }
-	|	yASSERT pslProp yREPORT ySTRING ';'	{ $$ = new AstPslAssert($1,$2,*$4); }
+pslDirOne:	yPSL_ASSERT pslProp ';'			{ $$ = new AstPslAssert($1,$2); }
+	|	yPSL_ASSERT pslProp yREPORT ySTRING ';'	{ $$ = new AstPslAssert($1,$2,*$4); }
 	|	yCOVER  pslProp ';'			{ $$ = new AstPslCover($1,$2); }
 	|	yCOVER  pslProp yREPORT ySTRING ';'	{ $$ = new AstPslCover($1,$2,*$4); }
 	;

test_c/Makefile_obj

@@ -34,6 +34,6 @@ ifeq ($(VM_TRACE),1)
 endif
 
 simx: sim_main.o $(SP_SRCS) $(VM_PREFIX)__ALL.a
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 
 sim_main.o: sim_main.cpp $(VM_PREFIX).h

test_regress/Makefile_obj

@@ -43,7 +43,7 @@ endif
 
 #Default compile, using normal make rules
 #$(VM_PREFIX): $(SP_SRCS) $(VK_OBJS)
-#	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+#	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 
 #Our own compile rules; Faster compile, all in one file
 $(VM_PREFIX)__ALLboth.cpp: $(VK_CLASSES_CPP) $(VK_SUPPORT_CPP)
@@ -54,5 +54,5 @@ $(VM_PREFIX)__ALLboth.o: $(VM_PREFIX)__ALLboth.cpp
 
 ifneq ($(MAKE_MAIN),0)
    $(VM_PREFIX): $(VM_PREFIX)__ALLboth.o
-	$(CXX) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
+	$(LINK) $(LDFLAGS) -g $^ $(LOADLIBES) $(LDLIBS) -o $@ $(LIBS) 2>&1 | c++filt
 endif

test_regress/driver.pl

@@ -197,13 +197,17 @@ sub new {
 	# VCS
 	vcs => 0,
 	vcs_flags => [split(/\s+/,"+cli -I +define+vcs+1 -q +v2k")],
+	vcs_flags2 => [],  # Overridden in some sim files
 	# NC
 	nc => 0,
-	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+nc=1 -q +assert +sv31a")],
+	nc_flags => [split(/\s+/,"+licqueue +nowarn+LIBNOU +define+nc=1 -q +assert +sv")],
+	nc_flags2 => [],  # Overridden in some sim files
 	# Verilator
 	'v3' => 0,
 	verilator_flags => [split(/\s+/,"-cc")],
+	verilator_flags2 => [],
 	verilator_make_gcc => 1,
+	verilated_debug => $Opt_Verilated_Debug,
 	stdout_filename => undef,	# Redirect stdout
 	@_};
     bless $self, $class;
@@ -289,8 +293,9 @@ sub compile {
 	$self->_make_top();
 	$self->_run(logfile=>"obj_dir/".$self->{name}."_vcs_compile.log",
 		    fails=>$param{fails},
-		    cmd=>["vcs",
+		    cmd=>[($ENV{VERILATOR_VCS}||"vcs"),
 			  @{$param{vcs_flags}},
+			  @{$param{vcs_flags2}},
 			  @{$param{v_flags}},
 			  @{$param{v_flags2}},
 			  $param{top_filename},
@@ -302,8 +307,9 @@ sub compile {
 	$self->_make_top();
 	$self->_run(logfile=>"obj_dir/".$self->{name}."_nc_compile.log",
 		    fails=>$param{fails},
-		    cmd=>["ncverilog",
+		    cmd=>[($ENV{VERILATOR_NCVERILOG}||"ncverilog"),
 			  @{$param{nc_flags}},
+			  @{$param{nc_flags2}},
 			  @{$param{v_flags}},
 			  @{$param{v_flags2}},
 			  $param{top_filename},
@@ -333,6 +339,7 @@ sub compile {
 	my @v3args = ("perl","../bin/verilator",
 		      "--prefix ".$self->{VM_PREFIX},
 		      @{$param{verilator_flags}},
+		      @{$param{verilator_flags2}},
 		      @{$param{v_flags}},
 		      @{$param{v_flags2}},
 		      $param{top_filename},
@@ -541,7 +548,7 @@ sub _make_main {
 	print $fh "int main(int argc, char **argv, char **env) {\n";
 	print $fh "    double sim_time = 1000;\n";
     }
-    print $fh "    Verilated::debug(".($Opt_Verilated_Debug?1:0).");\n";
+    print $fh "    Verilated::debug(".($self->{verilated_debug}?1:0).");\n";
     print $fh "    topp = new $VM_PREFIX (\"TOP\");\n";
     my $set;
     if ($self->sp) {
@@ -841,6 +848,24 @@ Run using Verilator.
 
 =back
 
+=head1 ENVIRONMENT
+
+=over 4
+
+=item SYSTEMC
+
+Root directory name of SystemC kit.
+
+=item VERILATOR_NCVERILOG
+
+Command to use to invoke ncverilog.
+
+=item VERILATOR_VCS
+
+Command to use to invoke VCS.
+
+=back
+
 =head1 SEE ALSO
 
 =head1 AUTHORS

test_regress/t/t_EXAMPLE.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // Use this file as a template for submitting bugs, etc.
@@ -7,57 +7,96 @@
 //	$finish
 // on success, or $stop.
 //
+// The code as shown applies a random vector to the Test
+// module, then calculates a CRC on the Test module's outputs.
+//
 // **If you do not wish for your code to be released to the public
-// please note it here**
+// please note it here, otherwise:**
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
 
 module t (/*AUTOARG*/
    // Inputs
    clk
    );
-
    input clk;
 
-   // Some inputs we'll set to random values
-   reg [31:0] in_a;
-   reg [31:0] in_b;
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
 
-   // Some arbitrary function for testing
-   // We'll test below that for each random in_a and in_b, we get a good out_a.
-   wire [31:0] out_x = (in_a ^ in_b);
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
 
-   integer cyc; initial cyc=1;
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0] 		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h4afe43fb79d7b71e
+
+   // Test loop
    always @ (posedge clk) begin
-      if (cyc!=0) begin
-	 cyc <= cyc + 1;
-	 $write("%d %x %x %x\n", cyc, in_a, in_b, out_x);
-	 if (cyc==1) begin
-	    // Assign inputs randomly
-	    in_a  <= 32'h89a14fab;
-	    in_b <= 32'h7ab512fa;
-	 end
-	 if (cyc==2) begin
-	    in_a  <= 32'hf4c11a42;
-	    in_b <= 32'h359967c6;
-	    // Verify output is correct
-            if (out_x != 32'hf3145d51) $stop;
-	 end
-	 if (cyc==3) begin
-	    in_a  <= 32'h58dca151;
-	    in_b <= 32'hdc687b27;
-            if (out_x != 32'hc1587d84) $stop;
-	 end
-	 if (cyc==4) begin
-	    in_a  <= 32'h09df0bbb;
-	    in_b <= 32'h0d0e7231;
-            if (out_x != 32'h84b4da76) $stop;
-	 end
-	 if (cyc==5) begin
-            if (out_x != 32'h04d1798a) $stop;
-	 end
-	 if (cyc==9) begin
-	    $write("*-* All Finished *-*\n");
-	    $finish;
-	 end
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
       end
    end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   // Replace this module with the device under test.
+   //
+   // Change the code in the t module to apply values to the inputs and
+   // merge the output values into the result vector.
+
+   input clk;
+   input  [31:0] in;   
+   output [31:0] out;
+
+   /*AUTOREG*/
+   // Beginning of automatic regs (for this module's undeclared outputs)
+   reg [31:0] 		out;
+   // End of automatics
+
+   always @(posedge clk) begin
+      out <= in;
+   end
 endmodule

test_regress/t/t_assert_basic.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'--assert':($Last_Self->{nc}?'+assert':'')],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+ok(1);
+1;

test_regress/t/t_assert_basic.v

@@ -0,0 +1,48 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+
+   reg 	 toggle;
+
+   integer cyc; initial cyc=1;
+   wire [7:0] cyc_copy = cyc[7:0];
+
+   always @ (negedge clk) begin
+      AssertionFalse1: assert (cyc<100);
+      assert (!(cyc==5) || toggle);
+      // FIX cover  {cyc==3 || cyc==4};
+      // FIX cover {cyc==9} report "DefaultClock,expect=1";
+      // FIX cover  {(cyc==5)->toggle} report "ToggleLogIf,expect=1";
+   end
+   
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+	 toggle <= !cyc[0];
+	 if (cyc==9) begin
+`ifdef FAILING_ASSERTIONS
+	    assert (0) else $info;
+	    assert (0) else $info("Info message");
+	    assert (0) else $info("Info message, cyc=%d", cyc);
+	    InWarningBlock: assert (0) else $warning("Warning....");
+	    InErrorBlock: assert (0) else $error("Error....");
+	    assert (0) else $fatal(1,"Fatal....");
+`endif
+	 end
+	 if (cyc==10) begin
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+
+endmodule

test_regress/t/t_assert_basic_cover.pl

@@ -0,0 +1,27 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_assert_basic.v");
+
+compile (
+	 v_flags2 => [$Last_Self->{v3}?'--assert --sp --coverage-user':''],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+#Needs work
+print "-Info:  NOT checking for coverage\n";
+#file_grep ($Last_Self->{coverage_filename}, qr/t=>'psl_cover',o=>'cover',c=>2\);/);
+#file_grep ($Last_Self->{coverage_filename}, qr/DefaultClock.*,c=>1\);/);
+#file_grep ($Last_Self->{coverage_filename}, qr/ToggleLogIf.*,c=>9\);/);
+
+ok(1);
+1;

test_regress/t/t_assert_basic_fail.pl

@@ -0,0 +1,23 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_assert_basic.v");
+
+compile (
+	 v_flags2 => ['+define+FAILING_ASSERTIONS',
+	              $Last_Self->{v3}?'--assert':($Last_Self->{nc}?'+assert':'')],
+	 fails => $Last_Self->{nc},
+	 );
+
+execute (
+	 fails => 1,
+	 );
+
+ok(1);
+1;

test_regress/t/t_assert_basic_off.pl

@@ -0,0 +1,21 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003-2007 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+top_filename("t/t_assert_basic.v");
+
+compile (
+	 v_flags2 => [],
+	 );
+
+execute (
+	 check_finished=>1,
+	 );
+
+ok(1);
+1;

test_regress/t/t_bitsel_loop.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -31,7 +31,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x/%x %x\n", q, qq, a);
+`endif
 	 if (cyc==1) begin
 	    a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
 	 end

test_regress/t/t_blocking.v

@@ -65,7 +65,6 @@ module t (/*AUTOARG*/
 	 end
 	 else if (_mode==4) begin
 	    if (mode_d3r != 8'd1) $stop;
-	    $write("[%0t] t_blocking: Passed\n", $time);
 	    $write("*-* All Finished *-*\n");
 	    $finish;
 	 end

test_regress/t/t_case_deep.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_case_deep.v

@@ -0,0 +1,342 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [33:0]  in = crc[33:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		code;			// From test of Test.v
+   wire [4:0]		len;			// From test of Test.v
+   wire			next;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .next			(next),
+	      .code			(code[31:0]),
+	      .len			(len[4:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[33:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {26'h0, next, len, code};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h5537fa30d49bf865
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   next, code, len,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input  [33:0] in;   
+   output 	 next;
+   output [31:0] code;
+   output [4:0]	 len;
+
+   /*AUTOREG*/
+   // Beginning of automatic regs (for this module's undeclared outputs)
+   reg [31:0]		code;
+   reg [4:0]		len;
+   reg			next;
+   // End of automatics
+
+/*
+#!/usr/bin/perl -w
+srand(5);
+my @used;
+pat:
+  for (my $pat=0; 1; ) {
+    last if $pat > 196;
+    my $len = int($pat / (6 + $pat/50)) + 4;  $len=20 if $len>20;
+    my ($try, $val, $mask);
+  try:
+    for ($try=0; ; $try++) {
+	next pat if $try>50;
+	$val = 0;
+	for (my $bit=23; $bit>(23-$len); $bit--) {
+	    my $b = int(rand()*2);
+	    $val |= (1<<$bit) if $b;
+	}
+	$mask = (1<<(23-$len+1))-1;
+	for (my $testval = $val; $testval <= ($val + $mask); $testval ++) {
+	    next try if $used[$testval];
+	}
+	last;
+    }
+    my $bits = "";
+    my $val2 = 0;
+    for (my $bit=23; $bit>(23-$len); $bit--) {
+	my $b = ($val & (1<<$bit));
+	$bits .= $b?'1':'0';
+    }
+    for (my $testval = $val; $testval <= ($val + $mask); $testval++) {
+	$used[$testval]= 1; #printf "U%08x\n", $testval;
+    }
+    if ($try<90) {
+	printf +("     24'b%s: {next, len, code} = {in[%02d], 5'd%02d, 32'd%03d};\n"
+		 ,$bits.("?"x(24-$len)), 31-$len, $len, $pat);
+	$pat++;
+    }
+}
+*/
+
+   always @* begin
+      next = 1'b0;
+      code = 32'd0;
+      len  = 5'b11111;
+      casez (in[31:8])
+	24'b1010????????????????????: {next, len, code} = {in[27], 5'd04, 32'd000};
+	24'b1100????????????????????: {next, len, code} = {in[27], 5'd04, 32'd001};
+	24'b0110????????????????????: {next, len, code} = {in[27], 5'd04, 32'd002};
+	24'b1001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd003};
+	24'b1101????????????????????: {next, len, code} = {in[27], 5'd04, 32'd004};
+	24'b0011????????????????????: {next, len, code} = {in[27], 5'd04, 32'd005};
+	24'b0001????????????????????: {next, len, code} = {in[27], 5'd04, 32'd006};
+	24'b10001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd007};
+	24'b01110???????????????????: {next, len, code} = {in[26], 5'd05, 32'd008};
+	24'b01000???????????????????: {next, len, code} = {in[26], 5'd05, 32'd009};
+	24'b00001???????????????????: {next, len, code} = {in[26], 5'd05, 32'd010};
+	24'b11100???????????????????: {next, len, code} = {in[26], 5'd05, 32'd011};
+	24'b01011???????????????????: {next, len, code} = {in[26], 5'd05, 32'd012};
+	24'b100001??????????????????: {next, len, code} = {in[25], 5'd06, 32'd013};
+	24'b111110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd014};
+	24'b010010??????????????????: {next, len, code} = {in[25], 5'd06, 32'd015};
+	24'b001011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd016};
+	24'b101110??????????????????: {next, len, code} = {in[25], 5'd06, 32'd017};
+	24'b111011??????????????????: {next, len, code} = {in[25], 5'd06, 32'd018};
+	24'b0111101?????????????????: {next, len, code} = {in[24], 5'd07, 32'd020};
+	24'b0010100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd021};
+	24'b0111111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd022};
+	24'b1011010?????????????????: {next, len, code} = {in[24], 5'd07, 32'd023};
+	24'b1000000?????????????????: {next, len, code} = {in[24], 5'd07, 32'd024};
+	24'b1011111?????????????????: {next, len, code} = {in[24], 5'd07, 32'd025};
+	24'b1110100?????????????????: {next, len, code} = {in[24], 5'd07, 32'd026};
+	24'b01111100????????????????: {next, len, code} = {in[23], 5'd08, 32'd027};
+	24'b00000110????????????????: {next, len, code} = {in[23], 5'd08, 32'd028};
+	24'b00000101????????????????: {next, len, code} = {in[23], 5'd08, 32'd029};
+	24'b01001100????????????????: {next, len, code} = {in[23], 5'd08, 32'd030};
+	24'b10110110????????????????: {next, len, code} = {in[23], 5'd08, 32'd031};
+	24'b00100110????????????????: {next, len, code} = {in[23], 5'd08, 32'd032};
+	24'b11110010????????????????: {next, len, code} = {in[23], 5'd08, 32'd033};
+	24'b010011101???????????????: {next, len, code} = {in[22], 5'd09, 32'd034};
+	24'b001000000???????????????: {next, len, code} = {in[22], 5'd09, 32'd035};
+	24'b010101111???????????????: {next, len, code} = {in[22], 5'd09, 32'd036};
+	24'b010101010???????????????: {next, len, code} = {in[22], 5'd09, 32'd037};
+	24'b010011011???????????????: {next, len, code} = {in[22], 5'd09, 32'd038};
+	24'b010100011???????????????: {next, len, code} = {in[22], 5'd09, 32'd039};
+	24'b010101000???????????????: {next, len, code} = {in[22], 5'd09, 32'd040};
+	24'b1111010101??????????????: {next, len, code} = {in[21], 5'd10, 32'd041};
+	24'b0010001000??????????????: {next, len, code} = {in[21], 5'd10, 32'd042};
+	24'b0101001101??????????????: {next, len, code} = {in[21], 5'd10, 32'd043};
+	24'b0010010100??????????????: {next, len, code} = {in[21], 5'd10, 32'd044};
+	24'b1011001110??????????????: {next, len, code} = {in[21], 5'd10, 32'd045};
+	24'b1111000011??????????????: {next, len, code} = {in[21], 5'd10, 32'd046};
+	24'b0101000000??????????????: {next, len, code} = {in[21], 5'd10, 32'd047};
+	24'b1111110000??????????????: {next, len, code} = {in[21], 5'd10, 32'd048};
+	24'b10110111010?????????????: {next, len, code} = {in[20], 5'd11, 32'd049};
+	24'b11110000011?????????????: {next, len, code} = {in[20], 5'd11, 32'd050};
+	24'b01001111011?????????????: {next, len, code} = {in[20], 5'd11, 32'd051};
+	24'b00101011011?????????????: {next, len, code} = {in[20], 5'd11, 32'd052};
+	24'b01010010100?????????????: {next, len, code} = {in[20], 5'd11, 32'd053};
+	24'b11110111100?????????????: {next, len, code} = {in[20], 5'd11, 32'd054};
+	24'b00100111001?????????????: {next, len, code} = {in[20], 5'd11, 32'd055};
+	24'b10110001010?????????????: {next, len, code} = {in[20], 5'd11, 32'd056};
+	24'b10000010000?????????????: {next, len, code} = {in[20], 5'd11, 32'd057};
+	24'b111111101100????????????: {next, len, code} = {in[19], 5'd12, 32'd058};
+	24'b100000111110????????????: {next, len, code} = {in[19], 5'd12, 32'd059};
+	24'b100000110010????????????: {next, len, code} = {in[19], 5'd12, 32'd060};
+	24'b100000111001????????????: {next, len, code} = {in[19], 5'd12, 32'd061};
+	24'b010100101111????????????: {next, len, code} = {in[19], 5'd12, 32'd062};
+	24'b001000001100????????????: {next, len, code} = {in[19], 5'd12, 32'd063};
+	24'b000001111111????????????: {next, len, code} = {in[19], 5'd12, 32'd064};
+	24'b011111010100????????????: {next, len, code} = {in[19], 5'd12, 32'd065};
+	24'b1110101111101???????????: {next, len, code} = {in[18], 5'd13, 32'd066};
+	24'b0100110101110???????????: {next, len, code} = {in[18], 5'd13, 32'd067};
+	24'b1111111011011???????????: {next, len, code} = {in[18], 5'd13, 32'd068};
+	24'b0101011011001???????????: {next, len, code} = {in[18], 5'd13, 32'd069};
+	24'b0010000101100???????????: {next, len, code} = {in[18], 5'd13, 32'd070};
+	24'b1111111101101???????????: {next, len, code} = {in[18], 5'd13, 32'd071};
+	24'b1011110010110???????????: {next, len, code} = {in[18], 5'd13, 32'd072};
+	24'b0101010111010???????????: {next, len, code} = {in[18], 5'd13, 32'd073};
+	24'b1111011010010???????????: {next, len, code} = {in[18], 5'd13, 32'd074};
+	24'b01010100100011??????????: {next, len, code} = {in[17], 5'd14, 32'd075};
+	24'b10110000110010??????????: {next, len, code} = {in[17], 5'd14, 32'd076};
+	24'b10111101001111??????????: {next, len, code} = {in[17], 5'd14, 32'd077};
+	24'b10110000010101??????????: {next, len, code} = {in[17], 5'd14, 32'd078};
+	24'b00101011001111??????????: {next, len, code} = {in[17], 5'd14, 32'd079};
+	24'b00100000101100??????????: {next, len, code} = {in[17], 5'd14, 32'd080};
+	24'b11111110010111??????????: {next, len, code} = {in[17], 5'd14, 32'd081};
+	24'b10110010100000??????????: {next, len, code} = {in[17], 5'd14, 32'd082};
+	24'b11101011101000??????????: {next, len, code} = {in[17], 5'd14, 32'd083};
+	24'b01010000011111??????????: {next, len, code} = {in[17], 5'd14, 32'd084};
+	24'b101111011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd085};
+	24'b101111010001100?????????: {next, len, code} = {in[16], 5'd15, 32'd086};
+	24'b100000111100111?????????: {next, len, code} = {in[16], 5'd15, 32'd087};
+	24'b001010101011000?????????: {next, len, code} = {in[16], 5'd15, 32'd088};
+	24'b111111100100001?????????: {next, len, code} = {in[16], 5'd15, 32'd089};
+	24'b001001011000010?????????: {next, len, code} = {in[16], 5'd15, 32'd090};
+	24'b011110011001011?????????: {next, len, code} = {in[16], 5'd15, 32'd091};
+	24'b111111111111010?????????: {next, len, code} = {in[16], 5'd15, 32'd092};
+	24'b101111001010011?????????: {next, len, code} = {in[16], 5'd15, 32'd093};
+	24'b100000110000111?????????: {next, len, code} = {in[16], 5'd15, 32'd094};
+	24'b0010010000000101????????: {next, len, code} = {in[15], 5'd16, 32'd095};
+	24'b0010010010101001????????: {next, len, code} = {in[15], 5'd16, 32'd096};
+	24'b1111011010110010????????: {next, len, code} = {in[15], 5'd16, 32'd097};
+	24'b0010010001100100????????: {next, len, code} = {in[15], 5'd16, 32'd098};
+	24'b0101011101110100????????: {next, len, code} = {in[15], 5'd16, 32'd099};
+	24'b0101011010001111????????: {next, len, code} = {in[15], 5'd16, 32'd100};
+	24'b0010000110011111????????: {next, len, code} = {in[15], 5'd16, 32'd101};
+	24'b0101010010000101????????: {next, len, code} = {in[15], 5'd16, 32'd102};
+	24'b1110101011000000????????: {next, len, code} = {in[15], 5'd16, 32'd103};
+	24'b1111000000110010????????: {next, len, code} = {in[15], 5'd16, 32'd104};
+	24'b0111100010001101????????: {next, len, code} = {in[15], 5'd16, 32'd105};
+	24'b00100010110001100???????: {next, len, code} = {in[14], 5'd17, 32'd106};
+	24'b00100010101101010???????: {next, len, code} = {in[14], 5'd17, 32'd107};
+	24'b11111110111100000???????: {next, len, code} = {in[14], 5'd17, 32'd108};
+	24'b00100000111010000???????: {next, len, code} = {in[14], 5'd17, 32'd109};
+	24'b00100111011101001???????: {next, len, code} = {in[14], 5'd17, 32'd110};
+	24'b11111110111000011???????: {next, len, code} = {in[14], 5'd17, 32'd111};
+	24'b11110001101000100???????: {next, len, code} = {in[14], 5'd17, 32'd112};
+	24'b11101011101011101???????: {next, len, code} = {in[14], 5'd17, 32'd113};
+	24'b01010000100101011???????: {next, len, code} = {in[14], 5'd17, 32'd114};
+	24'b00100100110011001???????: {next, len, code} = {in[14], 5'd17, 32'd115};
+	24'b01001110010101000???????: {next, len, code} = {in[14], 5'd17, 32'd116};
+	24'b010011110101001000??????: {next, len, code} = {in[13], 5'd18, 32'd117};
+	24'b111010101110010010??????: {next, len, code} = {in[13], 5'd18, 32'd118};
+	24'b001001001001111000??????: {next, len, code} = {in[13], 5'd18, 32'd119};
+	24'b101111000110111101??????: {next, len, code} = {in[13], 5'd18, 32'd120};
+	24'b101101111010101001??????: {next, len, code} = {in[13], 5'd18, 32'd121};
+	24'b111101110010111110??????: {next, len, code} = {in[13], 5'd18, 32'd122};
+	24'b010100100011010000??????: {next, len, code} = {in[13], 5'd18, 32'd123};
+	24'b001001001111011001??????: {next, len, code} = {in[13], 5'd18, 32'd124};
+	24'b010100110010001001??????: {next, len, code} = {in[13], 5'd18, 32'd125};
+	24'b111010110000111000??????: {next, len, code} = {in[13], 5'd18, 32'd126};
+	24'b111010110011000101??????: {next, len, code} = {in[13], 5'd18, 32'd127};
+	24'b010100001000111001??????: {next, len, code} = {in[13], 5'd18, 32'd128};
+	24'b1000001011000110100?????: {next, len, code} = {in[12], 5'd19, 32'd129};
+	24'b0010010111001110110?????: {next, len, code} = {in[12], 5'd19, 32'd130};
+	24'b0101011001000001101?????: {next, len, code} = {in[12], 5'd19, 32'd131};
+	24'b0101000010010101011?????: {next, len, code} = {in[12], 5'd19, 32'd132};
+	24'b1111011111101001101?????: {next, len, code} = {in[12], 5'd19, 32'd133};
+	24'b1011001000101010110?????: {next, len, code} = {in[12], 5'd19, 32'd134};
+	24'b1011000001000100001?????: {next, len, code} = {in[12], 5'd19, 32'd135};
+	24'b1110101100010011001?????: {next, len, code} = {in[12], 5'd19, 32'd136};
+	24'b0010010111010111110?????: {next, len, code} = {in[12], 5'd19, 32'd137};
+	24'b0010010001100111100?????: {next, len, code} = {in[12], 5'd19, 32'd138};
+	24'b1011001011100000101?????: {next, len, code} = {in[12], 5'd19, 32'd139};
+	24'b1011000100010100101?????: {next, len, code} = {in[12], 5'd19, 32'd140};
+	24'b1111111001000111011?????: {next, len, code} = {in[12], 5'd19, 32'd141};
+	24'b00100010111101101101????: {next, len, code} = {in[11], 5'd20, 32'd142};
+	24'b10000010101010101101????: {next, len, code} = {in[11], 5'd20, 32'd143};
+	24'b10110010100101001101????: {next, len, code} = {in[11], 5'd20, 32'd144};
+	24'b01010110111100010000????: {next, len, code} = {in[11], 5'd20, 32'd145};
+	24'b10110111110011001001????: {next, len, code} = {in[11], 5'd20, 32'd146};
+	24'b11111101101100100101????: {next, len, code} = {in[11], 5'd20, 32'd147};
+	24'b10110000010100100001????: {next, len, code} = {in[11], 5'd20, 32'd148};
+	24'b10110010011010110110????: {next, len, code} = {in[11], 5'd20, 32'd149};
+	24'b01111001010000011000????: {next, len, code} = {in[11], 5'd20, 32'd150};
+	24'b11110110001011011011????: {next, len, code} = {in[11], 5'd20, 32'd151};
+	24'b01010000100100001011????: {next, len, code} = {in[11], 5'd20, 32'd152};
+	24'b10110001100101110111????: {next, len, code} = {in[11], 5'd20, 32'd153};
+	24'b10111100110111101000????: {next, len, code} = {in[11], 5'd20, 32'd154};
+	24'b01010001010111010000????: {next, len, code} = {in[11], 5'd20, 32'd155};
+	24'b01010100111110001110????: {next, len, code} = {in[11], 5'd20, 32'd156};
+	24'b11111110011001100111????: {next, len, code} = {in[11], 5'd20, 32'd157};
+	24'b11110111111101010001????: {next, len, code} = {in[11], 5'd20, 32'd158};
+	24'b10110000010111100000????: {next, len, code} = {in[11], 5'd20, 32'd159};
+	24'b01001111100001000101????: {next, len, code} = {in[11], 5'd20, 32'd160};
+	24'b01010010000111010110????: {next, len, code} = {in[11], 5'd20, 32'd161};
+	24'b11101010101011101111????: {next, len, code} = {in[11], 5'd20, 32'd162};
+	24'b11111110010011100011????: {next, len, code} = {in[11], 5'd20, 32'd163};
+	24'b01010111001111101111????: {next, len, code} = {in[11], 5'd20, 32'd164};
+	24'b10110001111111111101????: {next, len, code} = {in[11], 5'd20, 32'd165};
+	24'b10110001001100110000????: {next, len, code} = {in[11], 5'd20, 32'd166};
+	24'b11110100011000111101????: {next, len, code} = {in[11], 5'd20, 32'd167};
+	24'b00101011101110100011????: {next, len, code} = {in[11], 5'd20, 32'd168};
+	24'b01010000011011111110????: {next, len, code} = {in[11], 5'd20, 32'd169};
+	24'b00000111000010000010????: {next, len, code} = {in[11], 5'd20, 32'd170};
+	24'b00101010000011001000????: {next, len, code} = {in[11], 5'd20, 32'd171};
+	24'b01001110010100101110????: {next, len, code} = {in[11], 5'd20, 32'd172};
+	24'b11110000000010000000????: {next, len, code} = {in[11], 5'd20, 32'd173};
+	24'b01001101011001111001????: {next, len, code} = {in[11], 5'd20, 32'd174};
+	24'b11110111000111010101????: {next, len, code} = {in[11], 5'd20, 32'd175};
+	24'b01111001101001110110????: {next, len, code} = {in[11], 5'd20, 32'd176};
+	24'b11110000101011101111????: {next, len, code} = {in[11], 5'd20, 32'd177};
+	24'b00100100100110101010????: {next, len, code} = {in[11], 5'd20, 32'd178};
+	24'b11110001011011000011????: {next, len, code} = {in[11], 5'd20, 32'd179};
+	24'b01010111001000110011????: {next, len, code} = {in[11], 5'd20, 32'd180};
+	24'b01111000000100010101????: {next, len, code} = {in[11], 5'd20, 32'd181};
+	24'b00100101101011001101????: {next, len, code} = {in[11], 5'd20, 32'd182};
+	24'b10110010110000111001????: {next, len, code} = {in[11], 5'd20, 32'd183};
+	24'b10110000101010000011????: {next, len, code} = {in[11], 5'd20, 32'd184};
+	24'b00100100111110001101????: {next, len, code} = {in[11], 5'd20, 32'd185};
+	24'b01111001101001101011????: {next, len, code} = {in[11], 5'd20, 32'd186};
+	24'b01010001000000010001????: {next, len, code} = {in[11], 5'd20, 32'd187};
+	24'b11110101111111101110????: {next, len, code} = {in[11], 5'd20, 32'd188};
+	24'b10000010111110110011????: {next, len, code} = {in[11], 5'd20, 32'd189};
+	24'b00000100011110100111????: {next, len, code} = {in[11], 5'd20, 32'd190};
+	24'b11111101001111101100????: {next, len, code} = {in[11], 5'd20, 32'd191};
+	24'b00101011100011110000????: {next, len, code} = {in[11], 5'd20, 32'd192};
+	24'b00100100111001011001????: {next, len, code} = {in[11], 5'd20, 32'd193};
+	24'b10000010101000000100????: {next, len, code} = {in[11], 5'd20, 32'd194};
+	24'b11110001001000111100????: {next, len, code} = {in[11], 5'd20, 32'd195};
+	24'b10111100011010011001????: {next, len, code} = {in[11], 5'd20, 32'd196};
+	24'b000000??????????????????: begin
+	   casez (in[33:32])
+	     2'b1?:   {next, len, code} = {1'b0, 5'd18, 32'd197};
+	     2'b01:   {next, len, code} = {1'b0, 5'd19, 32'd198};
+	     2'b00:   {next, len, code} = {1'b0, 5'd19, 32'd199};
+	     default: ;
+	   endcase
+	end
+	default: ;
+      endcase
+   end
+endmodule

test_regress/t/t_case_default_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_default_bad.v:\d+: Multiple default statements in case statement.

test_regress/t/t_case_genx_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_genx_bad.v:\d+: Use of x/\? constant in generate case statement, \(no such thing as \'generate casez\'\)

test_regress/t/t_case_nest.v

@@ -19,7 +19,9 @@ module t (/*AUTOARG*/
    sub sub (.in(crc[23:0]), .out1(out1));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};
@@ -29,7 +31,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'h2e5cb972eb02b8a0) $stop;
+	 if (sum !== 64'h2e5cb972eb02b8a0) $stop;
       end
       else if (cyc==91) begin
       end

test_regress/t/t_case_wild.v

@@ -30,7 +30,7 @@ module t (/*AUTOARG*/
 	 sum <= 64'h0;
       end
       else if (cyc==90) begin
-	 if (sum != 64'hf0afc2bfa78277c5) $stop;
+	 if (sum !== 64'hf0afc2bfa78277c5) $stop;
       end
       else if (cyc==91) begin
       end

test_regress/t/t_case_x_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_case_x_bad.v:\d+: Use of x/. constant in case statement, \(perhaps intended casex/casez\)

test_regress/t/t_display.pl

@@ -15,7 +15,9 @@ execute (
 	 expect=>quotemeta(
 '[0] In TOP.v: Hi
 [0] In TOP.v.sub
+[0] In TOP.v.sub.subblock
 [0] In TOP.v.sub2
+[0] In TOP.v.sub2.subblock2
 [0] %X=0c %D=12 %0X=c %0O=14 %B=001100
 [0] %x=0c %d=12 %0x=c %0o=14 %b=001100
 [0] %x=00abbbbcccc %0x=abbbbcccc %o=00527356746314 %b=00000101010111011101110111100110011001100

test_regress/t/t_display.v

@@ -44,13 +44,23 @@ endmodule
 
 module sub;
    task write_m;
-      $write("[%0t] In %m\n", $time);
+      begin
+	 $write("[%0t] In %m\n", $time);
+	 begin : subblock
+	    $write("[%0t] In %m\n", $time);
+	 end
+      end
    endtask
 endmodule
 
 module sub2;
    // verilator no_inline_module
    task write_m;
-      $write("[%0t] In %m\n", $time);
+      begin
+	 $write("[%0t] In %m\n", $time);
+	 begin : subblock2
+	    $write("[%0t] In %m\n", $time);
+	 end
+      end
    endtask
 endmodule

test_regress/t/t_display_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_display_bad.v:\d+: Missing arguments for \$display format

test_regress/t/t_flag_werror_bad1.pl

@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_flag_werror.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-WIDTH: t/t_flag_werror.v:\d+: Operator ASSIGNW expects 4 bits on the Assign RHS, but Assign RHS.s CONST generates 6 bits.

test_regress/t/t_flag_werror_bad2.pl

@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_flag_werror.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 verilator_flags=> [qw(-sp -Werror-WIDTH)],
 	 expect=>

test_regress/t/t_for_count.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -34,6 +34,27 @@ module t (/*AUTOARG*/
       end
    end
 
+   // While loop
+   integer w;
+   initial begin
+      while (w<10) w=w+1;
+      if (w!=10) $stop;
+      while (w<20) begin w=w+2; end
+      while (w<20) begin w=w+99999; end  // NEVER
+      if (w!=20) $stop;
+   end
+
+   // Do-While loop
+   integer dw;
+   initial begin
+      do dw=dw+1; while (dw<10);
+      if (dw!=10) $stop;
+      do dw=dw+2; while (dw<20);
+      if (dw!=20) $stop;
+      do dw=dw+5; while (dw<20);  // Once
+      if (dw!=25) $stop;
+   end
+
    always @ (posedge clk) begin
       cam_lookup_hit_vector <= 0;
       if (cyc!=0) begin
@@ -49,7 +70,7 @@ module t (/*AUTOARG*/
 	    if (hit_count != 32'd5) $stop;
 	    if (wide_for_count != 32'h80) $stop;
 	 end
-	 if (cyc==4) begin
+	 if (cyc==9) begin
 	    $write("*-* All Finished *-*\n");
 	    $finish;
 	 end

test_regress/t/t_func_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_func_bad.v:\d+: Too few arguments in function call

test_regress/t/t_func_bad2.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can

test_regress/t/t_func_bad_width.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2003 by Wilson Snyder. This program is free software; you can
@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>$Last_Self->{v3},
 	 expect=>
 '%Warning-WIDTH: t/t_func_bad_width.v:\d+: Operator FUNCREF expects 40 bits on the Function Argument, but Function Argument.s VARREF generates 39 bits.

test_regress/t/t_func_crc.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
 	 );
 
 execute (

test_regress/t/t_func_endian.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_func_endian.v

@@ -0,0 +1,110 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
+   wire  	noswap = crc[32];
+   wire 	nibble = crc[33];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0] 		out;			// From test of Test.v
+   wire [31:0] 		swapped;		// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      .swapped			(swapped[31:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .noswap			(noswap),
+	      .nibble			(nibble),
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h89522c3f5e5ca324) $stop;
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out, swapped,
+   // Inputs
+   clk, noswap, nibble, in
+   );
+   input clk;
+
+   input noswap;
+   input nibble;
+
+   input  [31:0] in;   
+   output [31:0] out;
+   output [31:0] swapped;
+
+   function [7:0] EndianSwap;
+      input Nibble;
+      input [7:0] Data;
+      begin
+         EndianSwap = (Nibble ? { Data[0], Data[1], Data[2], Data[3],
+				  Data[4], Data[5], Data[6], Data[7] }
+                       : { 4'h0, Data[0], Data[1], Data[2], Data[3] });
+      end	
+   endfunction
+   
+   assign out[31:24] = (noswap ? in[31:24]
+			: EndianSwap(nibble, in[31:24]));
+   assign out[23:16] = (noswap ? in[23:16]
+			: EndianSwap(nibble, in[23:16]));
+   assign out[15:8]  = (noswap ? in[15:8]
+			: EndianSwap(nibble, in[15:8]));
+   assign out[7:0]   = (noswap ? in[7:0]
+			: EndianSwap(nibble, in[7:0]));
+   
+   reg [31:0] swapped;
+   always @(posedge clk) begin
+      swapped[31:24] <= EndianSwap(nibble, in[31:24]);
+      swapped[23:16] <= EndianSwap(nibble, in[23:16]);
+      swapped[15:8]  <= EndianSwap(nibble, in[15:8] );
+      swapped[7:0]   <= EndianSwap(nibble, in[7:0]  );
+   end
+endmodule

test_regress/t/t_func_graphcirc.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_func_graphcirc.v

@@ -0,0 +1,49 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2006 by Wilson Snyder.
+
+module t (clk);
+   input clk;
+
+   integer cyc; initial cyc=0;
+
+   always @(posedge clk) begin
+      cyc <= cyc + 1;
+      if (cyc == 1) begin
+	 ReadContDisps;
+      end
+      else if (cyc == 5) begin
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+`ifndef verilator
+      DispContDisps;
+`endif
+   end
+
+   task ReadContDisps;
+      begin
+	 $display("%m: Here: %d", cyc);
+      end
+   endtask
+
+   integer dindex;
+
+   task DispContDisps;
+      /* verilator public */
+      begin
+	 if (cyc >= 2) begin
+            if ( cyc >= 4 ) begin
+	       dindex = dindex + 2; //*** Error line
+	       $display("%m: DIndex increment %d", cyc);
+	       $c("cout<<\"Hello1?\"<<endl;");
+            end
+	    $c("cout<<\"Hello2?\"<<endl;");
+	    $c("cout<<\"Hello3?\"<<endl;");
+	 end
+      end
+   endtask
+
+endmodule

test_regress/t/t_gate_elim.v

@@ -31,7 +31,9 @@ module t (/*AUTOARG*/
    te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $display("%b",{qa,qb,qc,qd,qe});
+`endif
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
 	 if (cyc==1) begin

test_regress/t/t_gen_assign.v

@@ -25,7 +25,9 @@ module t (/*AUTOARG*/
 		    .Input		(Input[8:0]));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       if (cyc==0) begin
@@ -37,7 +39,7 @@ module t (/*AUTOARG*/
 	 sum <= {sum[30:0],sum[31]} ^ {23'h0, crc[8:0]};
       end
       else if (cyc==99) begin
-	 if (sum != 32'he8bbd130) $stop;
+	 if (sum !== 32'he8bbd130) $stop;
 	 $write("*-* All Finished *-*\n");
 	 $finish;
       end

test_regress/t/t_gen_forif.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 nc_flags2 => ['+access+r'],
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_gen_forif.v

@@ -0,0 +1,111 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] crc;
+   reg [63:0] sum;
+
+   wire [3:0] Value = crc[3:0];
+
+   wire [3:0] Result;
+   wire [3:0] Result2;
+
+   Testit testit (/*AUTOINST*/
+		  // Outputs
+		  .Result		(Result[3:0]),
+		  .Result2		(Result2[3:0]),
+		  // Inputs
+		  .clk			(clk),
+		  .Value		(Value[3:0]));
+
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x %x %x %x\n",$time, cyc, crc, Result, Result2);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= {56'h0, Result, Result2}
+	     ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("*-* All Finished *-*\n");
+	 $write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== 64'h4af37965592f64f9) $stop;
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   reg Internal;
+
+   assign Result = Internal ^ clk;
+  
+   always @(posedge clk)
+     Internal <= #1 Value;
+endmodule
+
+module Test_wrap1 (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   Test t (clk, Value, Result);
+endmodule
+	
+module Test_wrap2 (clk, Value, Result);
+   input clk;
+   input Value;
+   output Result;
+
+   Test t (clk, Value, Result);
+endmodule
+
+module Testit (clk, Value, Result, Result2);
+   input clk;
+   input [3:0] Value;
+   output [3:0] Result;
+   output [3:0] Result2;
+
+   genvar i;
+   generate
+      for (i = 0; i < 4; i = i + 1)
+	begin : a
+	   if ((i == 0) || (i == 2)) begin : gblk
+	     Test_wrap1 test (clk, Value[i] , Result[i]);
+	   end
+	   else begin : gblk
+	     Test_wrap2 test (clk, Value[i], Result[i]);
+	   end
+	end
+   endgenerate
+
+   assign Result2[0] = a[0].gblk.test.t.Internal;
+   assign Result2[1] = a[1].gblk.test.t.Internal;
+   assign Result2[2] = a[2].gblk.test.t.Internal;
+   assign Result2[3] = a[3].gblk.test.t.Internal;
+
+endmodule

test_regress/t/t_gen_var_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '.*%Error: t/t_gen_var_bad.v:\d+: Non-genvar used in generate for: i

test_regress/t/t_if_deep.pl

@@ -0,0 +1,19 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 verilator_flags2 => ["--compiler msvc"],  # We have deep expressions we want to test
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_if_deep.v

@@ -0,0 +1,141 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+   input clk;
+
+   integer 	cyc=0;
+   reg [63:0] 	crc;
+   reg [63:0] 	sum;
+
+   // Take CRC data and apply to testblock inputs
+   wire [31:0]  in = crc[31:0];
+
+   /*AUTOWIRE*/
+   // Beginning of automatic wires (for undeclared instantiated-module outputs)
+   wire [31:0]		out;			// From test of Test.v
+   // End of automatics
+
+   Test test (/*AUTOINST*/
+	      // Outputs
+	      .out			(out[31:0]),
+	      // Inputs
+	      .clk			(clk),
+	      .in			(in[31:0]));
+
+   // Aggregate outputs into a single result vector
+   wire [63:0] result = {32'h0, out};
+
+   // What checksum will we end up with
+`define EXPECTED_SUM 64'h966e272fd829e672
+
+   // Test loop
+   always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%x result=%x\n",$time, cyc, crc, result);
+`endif
+      cyc <= cyc + 1;
+      crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
+      sum <= result ^ {sum[62:0],sum[63]^sum[2]^sum[0]};
+      if (cyc==0) begin
+	 // Setup
+	 crc <= 64'h5aef0c8d_d70a4497;
+      end
+      else if (cyc<10) begin
+	 sum <= 64'h0;
+      end
+      else if (cyc<90) begin
+      end
+      else if (cyc==99) begin
+	 $write("[%0t] cyc==%0d crc=%x sum=%x\n",$time, cyc, crc, sum);
+	 if (crc !== 64'hc77bb9b3784ea091) $stop;
+	 if (sum !== `EXPECTED_SUM) $stop;
+	 $write("*-* All Finished *-*\n");
+	 $finish;
+      end
+   end
+
+endmodule
+
+module Test (/*AUTOARG*/
+   // Outputs
+   out,
+   // Inputs
+   clk, in
+   );
+
+   input clk;
+   input  [31:0] in;   
+   output [31:0] out;
+
+   /*AUTOREG*/
+   // Beginning of automatic regs (for this module's undeclared outputs)
+   reg [31:0]		out;
+   // End of automatics
+
+`ifdef verilator
+ `define dontOptimize $c1("1")
+`else
+ `define dontOptimize 1'b1
+`endif
+
+   always @(posedge clk) begin
+      out <= in;
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+      if (`dontOptimize) if (`dontOptimize) if (`dontOptimize) if (`dontOptimize)
+	if (in[0])
+	  out <= ~in;
+   end
+endmodule

test_regress/t/t_inst_array_bad.pl

@@ -8,6 +8,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 # General Public License or the Perl Artistic License.
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 fails=>1,
 	 expect=>
 '%Error: t/t_inst_array_bad.v:19: Port connection __pinNumber2 as part of a module instance array  requires 1 or 8 bits, but connection\'s VARREF generates 9 bits.

test_regress/t/t_inst_overwide_bad.pl

@@ -1,6 +1,6 @@
 #!/usr/bin/perl
 if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
-# $Id:$
+# $Id$
 # DESCRIPTION: Verilator: Verilog Test driver/expect definition
 #
 # Copyright 2004 by Wilson Snyder. This program is free software; you can
@@ -10,6 +10,7 @@ if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
 top_filename("t/t_inst_overwide.v");
 
 compile (
+	 v_flags2 => ["--lint-only"],
 	 make_top_shell=>0,
 	 verilator_flags=> [qw(-sp)],
 	 verilator_make_gcc=>0,

test_regress/t/t_inst_sv.pl

@@ -0,0 +1,18 @@
+#!/usr/bin/perl
+if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
+# $Id$
+# DESCRIPTION: Verilator: Verilog Test driver/expect definition
+#
+# Copyright 2003 by Wilson Snyder. This program is free software; you can
+# redistribute it and/or modify it under the terms of either the GNU
+# General Public License or the Perl Artistic License.
+
+compile (
+	 );
+
+execute (
+	 check_finished=>1,
+     );
+
+ok(1);
+1;

test_regress/t/t_inst_sv.v

@@ -0,0 +1,75 @@
+// $Id$
+// DESCRIPTION: Verilator: Verilog Test module
+//
+// This file ONLY is placed into the Public Domain, for any use,
+// without warranty, 2007 by Wilson Snyder.
+
+module t (/*AUTOARG*/
+   // Inputs
+   clk
+   );
+
+   input clk;
+   integer cyc; initial cyc=1;
+
+   supply0 [1:0] low;
+   supply1 [1:0] high;
+
+   reg [7:0] isizedwire;
+   reg ionewire;
+
+   wire oonewire;
+   wire [7:0]		osizedreg;		// From sub of t_inst_v2k_sub.v
+
+   t_inst sub
+     (
+      .osizedreg,
+      .oonewire,
+      // Inputs
+      .isizedwire			(isizedwire[7:0]),
+      .*
+      //.ionewire			(ionewire)
+      );
+
+   always @ (posedge clk) begin
+      if (cyc!=0) begin
+	 cyc <= cyc + 1;
+	 if (cyc==1) begin
+	    ionewire <= 1'b1;
+	    isizedwire <= 8'd8;
+	 end
+	 if (cyc==2) begin
+	    if (low != 2'b00) $stop;
+	    if (high != 2'b11) $stop;
+	    if (oonewire !== 1'b1) $stop;
+	    if (isizedwire !== 8'd8) $stop;
+	 end
+	 if (cyc==3) begin
+	    ionewire <= 1'b0;
+	    isizedwire <= 8'd7;
+	 end
+	 if (cyc==4) begin
+	    if (oonewire !== 1'b0) $stop;
+	    if (isizedwire !== 8'd7) $stop;
+	    $write("*-* All Finished *-*\n");
+	    $finish;
+	 end
+      end
+   end
+endmodule
+
+module t_inst
+  (
+   output reg [7:0] osizedreg,
+   output wire oonewire /*verilator public*/,
+   input [7:0] isizedwire,
+   input wire ionewire
+   );
+
+   assign oonewire = ionewire;
+
+   always @* begin
+      osizedreg = isizedwire;
+   end
+
+endmodule