Add --trace-depth option

git-svn-id: file://localhost/svn/verilator/trunk/verilator@876 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.63****
+
+***  Add --trace-depth option for minimizing VCD file size. [Emerson Suguimoto]
+
 * Verilator 3.632 1/17/2007
 
 ***  Add /*verilator isolate_assignments*/ attribute.  [Mike Shinkarovsky]

bin/verilator

@@ -449,6 +449,13 @@ Adds waveform tracing code to the model.  Having tracing compiled in may
 result in some small performance losses, even when waveforms are not turned
 on during model execution.
 
+=item --trace-depth I<levels>
+
+Specify the number of levels deep to enable tracing, for example
+--trace-level 1 to only see the top level's signals.  Defaults to the
+entire model.  Using a small number will decrease visibility, but greatly
+improve runtime and trace file size.
+
 =item --underline-zero
 
 Rarely needed.  Signals starting with a underline should be initialized to

src/V3Link.cpp

@@ -143,6 +143,13 @@ private:
 	if (!m_curVarsp) nodep->v3fatalSrc("Var not under module??\n");
 	nodep->iterateChildren(*this);
 	if (m_idState==ID_FIND) {
+	    // We used modTrace before leveling, and we may now
+	    // want to turn it off now that we know the levelizations
+	    if (v3Global.opt.traceDepth()
+		&& (m_modp->level()-1) > v3Global.opt.traceDepth()) {
+		m_modp->modTrace(false);
+		nodep->trace(false);
+	    }
 	    // Find under either a task or the module's vars
 	    AstNode* findidp = m_curVarsp->findIdName(nodep->name());
 	    AstVar* findvarp = findidp->castVar();

src/V3Options.cpp

@@ -353,6 +353,10 @@ void V3Options::parseOptsList(FileLine* fl, int argc, char** argv) {
 		shift;
 		m_outputSplitCFuncs = atoi(argv[i]);
 	    }
+	    else if ( !strcmp (sw, "-trace-depth") ) {
+		shift;
+		m_traceDepth = atoi(argv[i]);
+	    }
 	    else if ( !strcmp (sw, "-unroll-count") ) { // Undocumented optimization tweak
 		shift;
 		m_unrollCount = atoi(argv[i]);
@@ -587,6 +591,7 @@ V3Options::V3Options() {
     m_inlineMult = 2000;
     m_outputSplit = 0;
     m_outputSplitCFuncs = 0;
+    m_traceDepth = 0;
     m_unrollCount = 64;
     m_unrollStmts = 20;
 

src/V3Options.h

@@ -72,6 +72,7 @@ class V3Options {
     int		m_inlineMult;	// main switch: --inline-mult
     int		m_outputSplit;	// main switch: --output-split
     int		m_outputSplitCFuncs;// main switch: --output-split-cfuncs
+    int		m_traceDepth;	// main switch: --trace-depth
     int		m_unrollCount;	// main switch: --unroll-count
     int		m_unrollStmts;	// main switch: --unroll-stmts
 
@@ -155,6 +156,7 @@ class V3Options {
     int	   inlineMult() const { return m_inlineMult; }
     int	   outputSplit() const { return m_outputSplit; }
     int	   outputSplitCFuncs() const { return m_outputSplitCFuncs; }
+    int	   traceDepth() const { return m_traceDepth; }
     int	   unrollCount() const { return m_unrollCount; }
     int	   unrollStmts() const { return m_unrollStmts; }
 

test_regress/t/t_EXAMPLE.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // Use this file as a template for submitting bugs, etc.
@@ -29,7 +29,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%d %x %x %x\n", cyc, in_a, in_b, out_x);
+`endif
 	 if (cyc==1) begin
 	    // Assign inputs randomly
 	    in_a  <= 32'h89a14fab;

test_regress/t/t_bitsel_loop.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -31,7 +31,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x/%x %x\n", q, qq, a);
+`endif
 	 if (cyc==1) begin
 	    a = 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
 	 end

test_regress/t/t_blocking.v

@@ -65,7 +65,6 @@ module t (/*AUTOARG*/
 	 end
 	 else if (_mode==4) begin
 	    if (mode_d3r != 8'd1) $stop;
-	    $write("[%0t] t_blocking: Passed\n", $time);
 	    $write("*-* All Finished *-*\n");
 	    $finish;
 	 end

test_regress/t/t_case_nest.v

@@ -19,7 +19,9 @@ module t (/*AUTOARG*/
    sub sub (.in(crc[23:0]), .out1(out1));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x sum=%x out=%x\n",$time, cyc, crc, sum, out1);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       sum <= {sum[62:0], sum[63]^sum[2]^sum[0]} ^ {63'h0,out1};

test_regress/t/t_gate_elim.v

@@ -31,7 +31,9 @@ module t (/*AUTOARG*/
    te te (.clk(clk), .b(b), .vconst(vconst), .q(qe));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $display("%b",{qa,qb,qc,qd,qe});
+`endif
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
 	 if (cyc==1) begin

test_regress/t/t_gen_assign.v

@@ -25,7 +25,9 @@ module t (/*AUTOARG*/
 		    .Input		(Input[8:0]));
 
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write("[%0t] cyc==%0d crc=%x q=%x\n",$time, cyc, crc, sum);
+`endif
       cyc <= cyc + 1;
       crc <= {crc[62:0], crc[63]^crc[2]^crc[0]};
       if (cyc==0) begin

test_regress/t/t_math_cmp.v

@@ -119,9 +119,11 @@ module prover (
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       if (cyc>2) begin
-	 if (0) $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
-      		       index_a, index_b,
-      		       gt, gts, gte, gtes, lt, lts, lte, ltes);
+`ifdef TEST_VERBOSE
+	 $write("results[%d][%d] = 8'b%b_%b_%b_%b_%b_%b_%b_%b;\n",
+      		index_a, index_b,
+      		gt, gts, gte, gtes, lt, lts, lte, ltes);
+`endif
 	 exp = results[index_a][index_b];
 	 got   = {gt, gts, gte, gtes, lt, lts, lte, ltes};
 	 if (exp !== got) begin

test_regress/t/t_math_concat.v

@@ -53,7 +53,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x %x\n", q, i);
+`endif
 	 if (cyc==1) begin
 	    i <= 256'hed388e646c843d35de489bab2413d77045e0eb7642b148537491f3da147e7f26;
 	 end

test_regress/t/t_math_concat64.v

@@ -95,7 +95,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x %x\n", q1, i);
+`endif
 	 if (cyc==1) begin
 	    i <= 128'hed388e646c843d35de489bab2413d770;
 	 end

test_regress/t/t_math_imm.v

@@ -47,9 +47,11 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       crc <= {crc[6:0], ~^ {crc[7],crc[5],crc[4],crc[3]}};
-      if (0) $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
-		    LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
-		    LowLogicImm, HighLogicImm, LogicImm);
+`ifdef TEST_VERBOSE
+      $write("[%0t] cyc==%0d crc=%b %d.%d,%d.%d -> %x.%x -> %x\n",$time, cyc, crc,
+	     LowMaskSel_Top, HighMaskSel_Top, LowMaskSel_Bot, HighMaskSel_Bot,
+	     LowLogicImm, HighLogicImm, LogicImm);
+`endif
       if (cyc==0) begin
 	 // Single case
 	 crc <= 8'h0;

test_regress/t/t_math_pow.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -25,7 +25,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%0x %x %x\n", cyc, p, shifted);
+`endif
 	 // Constant versions
 	 if (61'h1 ** 21'h31 != 61'h1) $stop;
 	 if (61'h2 ** 21'h10 != 61'h10000) $stop;

test_regress/t/t_math_repl.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -53,7 +53,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%x %x %x %x %x\n", rf, rf2, dualasr, sl_mask, sr_mask);
+`endif
 	 if (cyc==1) begin
 	    biu <= 64'h12451282_abadee00;
 	    okidoki <= 1'b0;

test_regress/t/t_math_shift.v

@@ -28,7 +28,9 @@ module t (/*AUTOARG*/
    always @ (posedge clk) begin
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
+`ifdef TEST_VERBOSE
 	 $write("%d %x %x %x %x\n", cyc, left, right, qleft, qright);
+`endif
 	 if (cyc==1) begin
 	    amt <= 32'd0;
 	    if (5'b10110>>2  != 5'b00101) $stop;

test_regress/t/t_mem_slot.cpp

@@ -6,7 +6,9 @@ unsigned int Array[3];
 
 unsigned int
 StepSim (Vt_mem_slot *sim, unsigned int slot, unsigned int bit, unsigned int val, unsigned int rslot) {
+#ifdef TEST_VERBOSE
     printf ("StepSim: slot=%d bit=%d val=%d rslot=%d\n", slot, bit, val, rslot);
+#endif
 
     sim->SlotIdx      = slot;
     sim->BitToChange  = bit;

test_regress/t/t_order_doubleloop.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,

test_regress/t/t_select_set.v

@@ -1,4 +1,4 @@
-// $Id:$
+// $Id$
 // DESCRIPTION: Verilator: Verilog Test module
 //
 // This file ONLY is placed into the Public Domain, for any use,
@@ -12,7 +12,9 @@ module t (clk);
 
    integer cyc; initial cyc=1;
    always @ (posedge clk) begin
+`ifdef TEST_VERBOSE
       $write ("%x %x\n", cyc, addr);
+`endif
       if (cyc!=0) begin
 	 cyc <= cyc + 1;
 	 if (cyc==1) begin