Allow isolate_assignments on task input/outputs
git-svn-id: file://localhost/svn/verilator/trunk/verilator@880 77ca24e4-aefa-0310-84f0-b9a241c72d87
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@ -9,6 +9,8 @@ indicates the contributor was also the author of the fix; Thanks!
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**** Fix isolate_assignments when many signals per always. [Mike Shinkarovsky]
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**** Fix isolate_assignments across task temporaries. [Mike Shinkarovsky]
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* Verilator 3.632 1/17/2007
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*** Add /*verilator isolate_assignments*/ attribute. [Mike Shinkarovsky]
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@ -382,6 +382,14 @@ private:
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//nodep->v3warn(GENCLK,"Signal unoptimizable: Generated clock: "<<nodep->prettyName());
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} else if (nodep->varp()->isSigPublic()) {
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nodep->v3warn(UNOPT,"Signal unoptimizable: Feedback to public clock or circular logic: "<<nodep->prettyName());
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if (!nodep->fileline()->warnIsOff(V3ErrorCode::UNOPT)) {
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nodep->fileline()->warnOff(V3ErrorCode::UNOPT, true); // Complain just once
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// Give the user an example.
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bool tempWeight = (edgep && edgep->weight()==0);
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if (tempWeight) edgep->weight(1); // Else the below loop detect can't see the loop
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m_graph.reportLoops(&OrderEdge::followComboConnected, vertexp); // calls OrderGraph::loopsVertexCb
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if (tempWeight) edgep->weight(0);
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}
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} else {
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// We don't use UNOPT, as there are lots of V2 places where it was needed, that aren't any more
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// First v3warn not inside warnIsOff so we can see the suppressions with --debug
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@ -306,6 +306,7 @@ private:
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AstVar* newvarp = new AstVar (invarp->fileline(), AstVarType::BLOCKTEMP,
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name, invarp);
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newvarp->funcLocal(false);
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newvarp->propagateAttrFrom(invarp);
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m_modp->addStmtp(newvarp);
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AstVarScope* newvscp = new AstVarScope (newvarp->fileline(), m_scopep, newvarp);
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m_scopep->addVarp(newvscp);
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@ -628,7 +629,7 @@ private:
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if (!funcp) nodep->v3fatalSrc("unlinked");
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// Inline func refs in the function
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iterateIntoFTask(funcp);
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// Create output variabls
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// Create output variable
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string namePrefix = "__Vfunc_"+funcp->shortName()+"__"+cvtToStr(m_modNCalls++);
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AstVarScope* outvscp = createVarScope (funcp->fvarp()->castVar(),
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namePrefix+"__out");
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@ -54,7 +54,7 @@ module t (/*AUTOARG*/
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$write("*-* All Finished *-*\n");
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$write("[%0t] cyc==%0d crc=%x %x\n",$time, cyc, crc, sum);
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if (crc !== 64'hc77bb9b3784ea091) $stop;
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if (sum !== 64'he281f003f6dd16b2) $stop;
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if (sum !== 64'h649ee1713d624dd9) $stop;
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$finish;
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end
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end
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@ -90,15 +90,23 @@ module file (/*AUTOARG*/
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d = {crc[15:0],~c[31:16]};
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end
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default: begin
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b = ~crc;
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set_d(~c); // d = ~c;
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set_b_d(crc, c);
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end
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endcase
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end
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task set_d;
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input [31:0] to;
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d = to;
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task set_b_d;
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`ifdef ISOLATE
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input [31:0] t_crc /* verilator isolate_assignments*/;
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input [31:0] t_c /* verilator isolate_assignments*/;
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`else
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input [31:0] t_crc;
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input [31:0] t_c;
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`endif
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begin
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b = {t_crc[31:16],~t_crc[23:8]};
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d = {t_crc[31:16], ~t_c[23:8]};
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end
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endtask
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always @* begin
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@ -14,7 +14,7 @@ compile (
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);
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if ($Last_Self->{v3}) {
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file_grep ($Last_Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+1/i);
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file_grep ($Last_Self->{stats}, qr/Optimizations, isolate_assignments blocks\s+3/i);
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}
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execute (
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