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Add `begin_keywords support 

git-svn-id: file://localhost/svn/verilator/trunk/verilator@894 77ca24e4-aefa-0310-84f0-b9a241c72d87
This commit is contained in:
Wilson Snyder 2007-03-05 21:35:49 +00:00
parent c7d80f8cf8
commit fabbfbc46e
9 changed files with 150 additions and 12 deletions
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2
Changes
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@ -5,6 +5,8 @@ indicates the contributor was also the author of the fix; Thanks!
* Verilator 3.63**
*** Support Verilog 2005 `begin_keywords and `end_keywords.
*** Updated list of SystemVerilog keywords to correspond to IEEE 1800-2005.
*** Add /*verilator public_flat*/. [Eugene Weber]

13
bin/verilator
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@ -891,18 +891,25 @@ The target system may also require edits to the Makefiles, the simple
Makefiles produced by Verilator presume the target system is the same type
as the build system.
=head1 VERILOG 2001 SUPPORT
=head1 VERILOG 2001 (IEEE 1364-2001) SUPPORT
Verilator supports the more common Verilog 2001 language features. This
includes signed numbers, "always @*", comma separated sensitivity lists,
generate statements, multidimensional arrays, localparam, and C-style
declarations inside port lists.
=head1 SYSTEMVERILOG 3.1 SUPPORT
=head1 VERILOG 2005 (IEEE 1364-2005) SUPPORT
Verilator supports the `begin_keywords and `end_keywords compiler
directives.
Verilator treats the uwire keyword as if it were the normal wire keyword.
=head1 SYSTEMVERILOG (IEEE 1800-2005) SUPPORT
Verilator currently has very minimal support for SystemVerilog.
Verilator implement the full SystemVerilog 3.1 preprocessor subset,
Verilator implements the full SystemVerilog 1800-2005 preprocessor subset,
including function call-like preprocessor defines. Verilator also
implements $bits, $countones, $isunknown, $onehot, and $onehot0,
always_comb, always_ff, always_latch, and final.

4
src/V3Read.cpp
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@ -62,10 +62,10 @@ public:
// METHODS
void stateExitPsl() {
if (YY_START != PSL) yyerror("Internal error: Exiting PSL state when not in PSL state");
BEGIN S05;
yy_pop_state();
}
void statePushVlg() {
yy_push_state(S05);
yy_push_state(STATE_VERILOG_RECENT);
}
void statePop() {
yy_pop_state();

4
src/V3Read.h
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@ -39,6 +39,7 @@ class V3Read {
static V3Read* s_readp; // Current THIS, bison() isn't class based
FileLine* m_fileline; // Filename/linenumber currently active
bool m_inLibrary; // Currently reading a library vs. regular file
int m_inBeginKwd; // Inside a `begin_keywords
deque<string*> m_stringps; // Created strings for later cleanup
deque<V3Number*> m_numberps; // Created numbers for later cleanup
//int debug() { return 9; }
@ -54,6 +55,8 @@ protected:
static void incLineno() { s_readp->fileline()->incLineno(); }
static void verilatorCmtLint(const char* text, bool on);
static void verilatorCmtBad(const char* text);
static void pushBeginKeywords() { s_readp->m_inBeginKwd++; }
static bool popBeginKeywords() { if (s_readp->m_inBeginKwd) { s_readp->m_inBeginKwd--; return true; } else return false; }
public: // But for internal use only
static string* newString(const string& text) {
@ -94,6 +97,7 @@ public:
V3Read(AstNetlist* rootp) {
m_rootp = rootp; m_lexerp = NULL;
m_inLibrary = false;
m_inBeginKwd = 0;
}
~V3Read() {
for (deque<string*>::iterator it = m_stringps.begin(); it != m_stringps.end(); ++it) {

23
src/verilog.l
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@ -31,6 +31,8 @@
extern void yyerror(char*);
extern void yyerrorf(const char* format, ...);
#define STATE_VERILOG_RECENT S05 // State name for most recent Verilog Version
//======================================================================
#define NEXTLINE() {V3Read::incLineno();}
@ -101,7 +103,7 @@ escid \\[^ \t\f\r\n]+
%%
<INITIAL>.|\n {BEGIN S05; yyless(0); }
<INITIAL>.|\n {BEGIN STATE_VERILOG_RECENT; yyless(0); }
<V95,V01,V05,S05,PSL>{
{ws} ; /* ignore white-space */
@ -162,6 +164,10 @@ escid \\[^ \t\f\r\n]+
"signed" {yylval.fileline = CRELINE(); return ySIGNED;}
}
<V05,S05,PSL>{
"uwire" {yylval.fileline = CRELINE(); return yWIRE;}
}
<S05,PSL>{
"always_comb" {yylval.fileline = CRELINE(); return yALWAYS;}
"always_ff" {yylval.fileline = CRELINE(); return yALWAYS;}
@ -228,7 +234,7 @@ escid \\[^ \t\f\r\n]+
/*Entry into PSL; mode change */
<V95,V01,V05,S05>{
"psl" { BEGIN PSL; yylval.fileline = CRELINE(); return yPSL; }
"psl" { yy_push_state(PSL); yylval.fileline = CRELINE(); return yPSL; }
}
<PSL>{
@ -330,11 +336,6 @@ escid \\[^ \t\f\r\n]+
"use" {yyerrorf("Unsupported: Verilog 2001 reserved word not implemented: %s",yytext);}
}
/* Verilog 2005 */
<V05,S05,PSL>{
"uwire" {yyerrorf("Unsupported: Verilog 2005 reserved word not implemented: %s",yytext);}
}
/* System Verilog */
<S05,PSL>{
/* Note assert_strobe was in SystemVerilog 3.1, but removed for SystemVerilog 2005 */
@ -643,6 +644,14 @@ escid \\[^ \t\f\r\n]+
[ \t]*"`systemc_interface" { BEGIN SYSCINT; }
[ \t]*"`systemc_implementation" { BEGIN SYSCIMP; }
[ \t]*"`systemc_imp_header" { BEGIN SYSCIMPH; }
[ \t]*"`begin_keywords"[ \t]*\"1364-1995\" { yy_push_state(V95); V3Read::pushBeginKeywords();}
[ \t]*"`begin_keywords"[ \t]*\"1364-2001\" { yy_push_state(V01); V3Read::pushBeginKeywords();}
[ \t]*"`begin_keywords"[ \t]*\"1364-2001-noconfig\" { yy_push_state(V01); V3Read::pushBeginKeywords();}
[ \t]*"`begin_keywords"[ \t]*\"1364-2005\" { yy_push_state(V05); V3Read::pushBeginKeywords();}
[ \t]*"`begin_keywords"[ \t]*\"1800-2005\" { yy_push_state(S05); V3Read::pushBeginKeywords();}
[ \t]*"`end_keywords" { yy_pop_state(); if (!V3Read::popBeginKeywords()) yyerrorf("`end_keywords when not inside `begin_keywords block"); }
"`line"[ \t][^\n]*\n {V3Read::ppline(yytext);}
}

18
test_regress/t/t_func_graphcirc.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

49
test_regress/t/t_func_graphcirc.v Normal file
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@ -0,0 +1,49 @@
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2006 by Wilson Snyder.
module t (clk);
input clk;
integer cyc; initial cyc=0;
always @(posedge clk) begin
cyc <= cyc + 1;
if (cyc == 1) begin
ReadContDisps;
end
else if (cyc == 5) begin
$write("*-* All Finished *-*\n");
$finish;
end
`ifndef verilator
DispContDisps;
`endif
end
task ReadContDisps;
begin
$display("%m: Here: %d", cyc);
end
endtask
integer dindex;
task DispContDisps;
/* verilator public */
begin
if (cyc >= 2) begin
if ( cyc >= 4 ) begin
dindex = dindex + 2; //*** Error line
$display("%m: DIndex increment %d", cyc);
$c("cout<<\"Hello1?\"<<endl;");
end
$c("cout<<\"Hello2?\"<<endl;");
$c("cout<<\"Hello3?\"<<endl;");
end
end
endtask
endmodule

18
test_regress/t/t_preproc_kwd.pl Executable file
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@ -0,0 +1,18 @@
#!/usr/bin/perl
if (!$::Driver) { use FindBin; exec("./driver.pl", @ARGV, $0); die; }
# $Id$
# DESCRIPTION: Verilator: Verilog Test driver/expect definition
#
# Copyright 2003 by Wilson Snyder. This program is free software; you can
# redistribute it and/or modify it under the terms of either the GNU
# General Public License or the Perl Artistic License.
compile (
);
execute (
check_finished=>1,
);
ok(1);
1;

31
test_regress/t/t_preproc_kwd.v Normal file
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@ -0,0 +1,31 @@
// $Id$
// DESCRIPTION: Verilator: Verilog Test module
//
// This file ONLY is placed into the Public Domain, for any use,
// without warranty, 2007 by Wilson Snyder.
module t (/*AUTOARG*/
// Inputs
clk
);
input clk;
`begin_keywords "1364-1995"
integer signed; initial signed = 1;
`end_keywords
`begin_keywords "1364-2001"
integer bit; initial bit = 1;
`end_keywords
`begin_keywords "1364-2005"
integer final; initial final = 1;
`begin_keywords "1800-2005"
final begin
$write("*-* All Finished *-*\n");
end
`end_keywords
`end_keywords
initial begin
$finish;
end
endmodule