Fix dotted references under other dotteds

git-svn-id: file://localhost/svn/verilator/trunk/verilator@904 77ca24e4-aefa-0310-84f0-b9a241c72d87

Changes

@@ -3,6 +3,10 @@ Revision history for Verilator
 The contributors that suggested a given feature are shown in [].  [by ...]
 indicates the contributor was also the author of the fix; Thanks!
 
+* Verilator 3.64**
+
+**** Fix dotted bit reference to local memory.  [Eugene Weber]
+
 * Verilator 3.640 3/12/2007
 
 ***  Support Verilog 2005 `begin_keywords and `end_keywords.

nodist/invoke_ncverilog

@@ -0,0 +1,70 @@
+#!/usr/bin/perl -w
+# $Id$
+######################################################################
+#
+# Copyright 2007-2007 by Wilson Snyder <wsnyder@wsnyder.org>.  This
+# program is free software; you can redistribute it and/or modify it under
+# the terms of either the GNU Lesser General Public License or the Perl
+# Artistic License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+######################################################################
+
+require 5.006_001;
+use strict;
+
+#======================================================================
+# main
+
+delete $ENV{MODULE_VERSION};
+_setup_modules();
+module('add','cadence_verif');
+exec('ncverilog',@ARGV);
+
+#######################################################################
+# Modules package
+
+sub _setup_modules {
+    # Load the 'module' command into the environment
+    my $init = "/sicortex/$ENV{DIRPROJECT_ARCH}/lib/Modules/default/init/perl";
+    (-f $init) or die "%Error: Script not found: $init,";
+    require $init;
+}
+
+#######################################################################
+__END__
+
+=pod
+
+=head1 NAME
+
+invoke_ncverilog - Invoke tool under "modules" command
+
+=head1 SYNOPSIS
+
+  invoke_ncverilog  {ncv arguments}
+
+=head1 DESCRIPTION
+
+=head1 DISTRIBUTION
+
+Copyright 2007-2007 by Wilson Snyder.  This package is free software; you
+can redistribute it and/or modify it under the terms of either the GNU
+Lesser General Public License or the Perl Artistic License.
+
+=head1 AUTHORS
+
+Wilson Snyder <wsnyder@wsnyder.org>
+
+=head1 SEE ALSO
+
+=cut
+
+######################################################################
+### Local Variables:
+### compile-command: "./invoke_ncverilog -help"
+### End:

src/V3LinkParse.cpp

@@ -89,6 +89,10 @@ private:
 	// VarRef: Parse its reference
 	UINFO(5,"   "<<nodep<<endl);
 	// May be a varref inside a select, etc, so save state and recurse
+	string		oldText = m_dotText;
+	bool		oldDot = m_inModDot;
+	AstParseRefExp  oldExp = m_exp;
+	AstText*	oldBasep = m_baseTextp;
 	{
 	    // Replace the parsed item with its child IE the selection tree down to the varref itself
 	    // Do this before iterating, so we don't have to process the edited tree twice
@@ -117,8 +121,14 @@ private:
 	    } else {
 		nodep->v3fatalSrc("Unknown ParseRefExp type\n");
 	    }
+	    nodep->deleteTree(); nodep=NULL;
+	}
+	if (m_exp != AstParseRefExp::FUNC) {  // Fuctions need to look at the name themself
+	    m_dotText = oldText;
+	    m_inModDot = oldDot;
+	    m_exp = oldExp;
+	    m_baseTextp = oldBasep;
 	}
-	nodep->deleteTree(); nodep=NULL;
     }
     virtual void visit(AstDot* nodep, AstNUser*) {
 	UINFO(5,"     "<<nodep<<endl);

test_regress/driver.pl

@@ -292,7 +292,7 @@ sub compile {
 	$self->_make_top();
 	$self->_run(logfile=>"obj_dir/".$self->{name}."_vcs_compile.log",
 		    fails=>$param{fails},
-		    cmd=>["vcs",
+		    cmd=>[($ENV{VERILATOR_VCS}||"vcs"),
 			  @{$param{vcs_flags}},
 			  @{$param{vcs_flags2}},
 			  @{$param{v_flags}},
@@ -306,7 +306,7 @@ sub compile {
 	$self->_make_top();
 	$self->_run(logfile=>"obj_dir/".$self->{name}."_nc_compile.log",
 		    fails=>$param{fails},
-		    cmd=>["ncverilog",
+		    cmd=>[($ENV{VERILATOR_NCVERILOG}||"ncverilog"),
 			  @{$param{nc_flags}},
 			  @{$param{nc_flags2}},
 			  @{$param{v_flags}},
@@ -846,6 +846,24 @@ Run using Verilator.
 
 =back
 
+=head1 ENVIRONMENT
+
+=over 4
+
+=item SYSTEMC
+
+Root directory name of SystemC kit.
+
+=item VERILATOR_NCVERILOG
+
+Command to use to invoke ncverilog.
+
+=item VERILATOR_VCS
+
+Command to use to invoke VCS.
+
+=back
+
 =head1 SEE ALSO
 
 =head1 AUTHORS

test_regress/t/t_var_dotted.v

@@ -16,6 +16,8 @@ module t (/*AUTOARG*/
    wire [31:0] outb1c0;
    wire [31:0] outb1c1;
 
+   reg [7:0]   lclmem [7:0];
+
    ma ma0 (.outb0c0(outb0c0), .outb0c1(outb0c1),
 	   .outb1c0(outb1c0), .outb1c1(outb1c1)
 	   );
@@ -25,7 +27,6 @@ module t (/*AUTOARG*/
 
    input clk;
    integer cyc=1;
-
    always @ (posedge clk) begin
       cyc <= cyc + 1;
       //$write("[%0t] cyc%0d: %0x %0x %0x %0x\n", $time, cyc, outb0c0, outb0c1, outb1c0, outb1c1);
@@ -45,12 +46,17 @@ module t (/*AUTOARG*/
 	 ma0.mb1.mc1.out <= ma0.mb1.mc1.out + 32'h100;
       end
       if (cyc==4) begin
+	 // Can we do dotted's inside array sels?
+	 ma0.rmtmem[ma0.mb0.mc0.out[2:0]] = 8'h12;
+	 lclmem[ma0.mb0.mc0.out[2:0]] = 8'h24;
 	 if (outb0c0 != 32'h100) $stop;
 	 if (outb0c1 != 32'h101) $stop;
 	 if (outb1c0 != 32'h110) $stop;
 	 if (outb1c1 != 32'h111) $stop;
       end
       if (cyc==5) begin
+	 if (ma0.rmtmem[ma0.mb0.mc0.out[2:0]] != 8'h12) $stop;
+	 if (lclmem[ma0.mb0.mc0.out[2:0]] != 8'h24) $stop;
 	 if (outb0c0 != 32'h1100) $stop;
 	 if (outb0c1 != 32'h2101) $stop;
 	 if (outb1c0 != 32'h2110) $stop;
@@ -97,6 +103,9 @@ module ma (
     output wire [31:0] outb1c1
 	   );
    `INLINE_MODULE
+
+     reg [7:0] rmtmem [7:0];
+
    mb #(0) mb0 (.outc0(outb0c0), .outc1(outb0c1));
    mb #(1) mb1 (.outc0(outb1c0), .outc1(outb1c1));
 endmodule