Commit Graph

9151 Commits

Author SHA1 Message Date
Wilson Snyder 2309d52fd6 Tests: Cleanup t_uvm_dpi. No test change. 2026-02-19 07:05:33 -05:00
Ryszard Rozak ff3028aca3
Support `disable iff` with sequences (#7090) 2026-02-19 11:33:30 +01:00
Yilou Wang 0e26b049ea
Support function calls with random arguments in constraints (#7061) (#7083) 2026-02-19 15:37:55 +05:30
Ryszard Rozak f843780aad
Add UNSUPPORTED on $sampled in sensitivity list (#7093) 2026-02-19 08:36:21 +01:00
Wilson Snyder 702d6ede09 Fix time to not advance after `$finish` (#7095).
Fixes #7095.
2026-02-18 19:36:36 -05:00
Wilson Snyder 3b7dfce6f5 Commentary: Changes update 2026-02-18 19:30:34 -05:00
Geza Lore 2cd8dc6cf7
Optimize functions inlined from packages in Dfg (#7091) 2026-02-18 19:11:33 +00:00
Todd Strader cf1de0b9a8
Fix interface internal type reference (#6920) (#6966) 2026-02-18 09:38:42 +05:30
Artur Bieniek da28c67e60
Fix #0 delays to control fork scheduling (#6730 repair) (#6891)
Signed-off-by: Artur Bieniek <abieniek@internships.antmicro.com>
2026-02-17 21:51:11 -05:00
Geza Lore 7176bdcff6
Optimize always blocks using local temporary variables in Dfg (#7085)
Enable synthesis of blocks that use a variable only within certain
branches, if that variable is not externally observable.
2026-02-17 20:00:55 +00:00
Ryszard Rozak 5d0352ab46
Fix conditional expressions in constraints (#7087) 2026-02-17 11:40:15 -05:00
Wilson Snyder 81d1d79585 Tests: Cleanup t_cover_assert 2026-02-17 08:47:43 -05:00
Wilson Snyder 089672b200 Tests: Improve t_lint_unused_func_bad.v 2026-02-17 06:20:42 -05:00
Wilson Snyder 9049c93009 Internals: Call common V3NUmber function to zero data type. Cleanup chandle clearling. 2026-02-17 06:18:57 -05:00
Geza Lore a1a9147267
Optimize straight line code in Dfg always (#7084) 2026-02-17 11:17:52 +00:00
Geza Lore 5834f22944
Optimize logic and variable removal early in Dfg (#7081)
After conversion of Ast to Dfg, but before synthesizing AstAlways into
primitives, run a pass to remove variables that are not observable, and
all logic that only computes such variables. This can get rid of a lot
of content early so we don't build redundant Dfgs, and also enables
synthesizing always blocks that use temporaries only in some branches,
which will come in a follow up.
2026-02-17 08:28:06 +00:00
Wilson Snyder ed2f018729 Tests: Improve t_var_static_assign_decl_bad 2026-02-17 02:18:56 -05:00
Wilson Snyder 7182e8d937 Internals: Track what variables get user initial assignment. 2026-02-17 02:05:05 -05:00
Wilson Snyder 6c5dee5043 Change automatic variables to not be traced. 2026-02-17 01:38:39 -05:00
Veripool API Bot 300be3e388 Verilog format 2026-02-16 23:21:53 -05:00
Wilson Snyder 1f157b36f5 Commentary: Changes update 2026-02-16 23:19:19 -05:00
Yilou Wang ed3aa43657
Fix enum variables in constraint solver producing invalid enum values (#7058) (#7065) 2026-02-16 22:44:38 -05:00
Yilou Wang 4357aee09a
Fix randomize() on null object handle crashing instead of returning 0 (#7059) (#7066) 2026-02-16 22:43:57 -05:00
Yilou Wang 5173f7e42f
Fix inside operator crash with impure expression and unsized range literals (#7063) (#7067) 2026-02-17 08:33:31 +05:30
Yilou Wang 994ef82e76
Support unique constraint on explicit array element subsets (#7057) (#7064) 2026-02-16 19:46:46 -05:00
Artur Bieniek 7fc428f518
Fix randomize() null pointer dereference (#7026) 2026-02-16 19:43:59 -05:00
Ryszard Rozak 8491d6a80c
Support force assignments to unpacked structs (#7060) 2026-02-17 05:35:07 +05:30
Wilson Snyder c21498293e Internals: Minor cleanups preparing for initialization fixes. 2026-02-16 08:10:29 -05:00
Wilson Snyder 14a94b6de9 Internals: Add addNextNull. No functional change intended. 2026-02-16 08:09:29 -05:00
Kamil Danecki 821eacebea
Support power expressions with constant exponent in constraints (#7073) 2026-02-16 06:01:24 -05:00
Srinivasan Venkataramanan 7c1b348b41 Support `$get_initial_random_seed` (#7056) (#7069).
Fixes #7056.
2026-02-16 05:57:44 -05:00
Wilson Snyder 28d04c809f Commentary: Changes update 2026-02-16 05:38:03 -05:00
Geza Lore 505d33b35a
Support #0 delays with IEEE-1800 compliant semantics (#7079)
This patch adds IEEE-1800 compliant scheduling support for the Inactive
scheduling region used for #0 delays.

Implementing this requires that **all** IEEE-1800 active region events
are placed in the internal 'act' section. This has simulation
performance implications. It prevents some optimizations (e.g.
V3LifePost), which reduces single threaded performance. It also reduces
the available work and parallelism in the internal 'nba' section, which
reduced the effectiveness of multi-threading severely.

Performance impact on RTLMeter when using scheduling adjusted to support
proper #0 delays is ~10-20% slowdown in single-threaded mode, and ~100%
(2x slower) with --threads 4.

To avoid paying this performance penalty unconditionally, the scheduling
is only adjusted if either:
1. The input contains a statically known #0 delay
2. The input contains a variable #x delay unknown at compile time

If no #0 is present, but #x variable delays are, a ZERODLY warning is
issued advising the use of '--no-sched-zero-delay' which is a promise
by the user that none of the variable delays will evaluate to a zero
delay at run-time. This warning is turned off if '--sched-zero-delay'
is explicitly given. This is similar to the '--timing' option.

If '--no-sched-zero-delay' was used at compile time, then executing
a zero delay will fail at runtime.

A ZERODLY warning is also issued if a static #0 if found, but the user
specified '--no-sched-zero-delay'. In this case the scheduling is not
adjusted to support #0, so executing it will fail at runtime. Presumably
the user knows it won't be executed.

The intended behaviour with all this is the following:

No #0, no #var in the design (#constant is OK)
-> Same as current behaviour, scheduling not adjusted,
   same code generated as before

Has static #0 and '--no-sched-zero-delay' is NOT given:
-> No warnings, scheduling adjusted so it just works, runs slow

Has static #0 and '--no-sched-zero-delay' is given:
-> ZERODLY on the #0, scheduling not adjusted, fails at runtime if hit

No static #0, but has #var and no option is given:
-> ZERODLY on the #var advising use of '--no-sched-zero-delay' or
   '--sched-zero-delay' (similar to '--timing'), scheduling adjusted
   assuming it can be a zero delay and it just works

No static #0, but has #var and '--no-sched-zero-delay' is given:
-> No warning, scheduling not adjusted, fails at runtime if zero delay

No static #0, but has #var and '--sched-zero-delay' is given:
-> No warning, scheduling adjusted so it just works
2026-02-16 03:55:55 +00:00
Geza Lore a0b89dde8e
Internals: Make AstCAwait an AstNodeStmt (#6280) (#7078)
AstCAwait is only ever uses in statement position, so model it as a
statement. We should never ever have a coroutine that returns a value.
There is no need for it in SV, nor should we rely on it for internals.

Also reworks the fix for V3Life incorrectly constant propagating the
beforeTrig functions (#7072). The property that upsets V3Life is that
a function:
1. Is called from multiple static call sites (multiple AstCCall)
2. Reads model state directly (AstVarRef to non-locals/arguments)

Such function can only be created internally after scheduling (V3Task
throws an unsupported error on a non-inlined function that reads model
state), so added a flag to AstCFunc to mark the dangerous ones for
V3Life.
2026-02-14 20:15:32 +00:00
Geza Lore be27811a10
Optimize: Remove redundant variables during Dfg Peephole pass (#7076)
Many rules in the Dfg Peephole pass check if a node has more than one
sinks. Redundant variables that will ultimately be removed can prevent
these from matching. Remove such variables during the Peeophole pass
itself to enable more matches.
2026-02-14 12:33:20 +00:00
Geza Lore a45a058b09
Optimize additional DFG peephole Shift and Concat patterns (#7077) 2026-02-14 07:25:17 -05:00
Geza Lore e0c626e48a
Fix constant propagating DPI-written variables (#7074) 2026-02-13 18:28:14 +00:00
Igor Zaworski 7d71c3bb76
Fix of event triggering with V3Life (#6932 effect) (#7068 partial) (#7072) 2026-02-13 11:01:19 -05:00
Geza Lore 0aaf17acfd Internals: Add referencing flags in Dfg dumps 2026-02-13 14:20:38 +00:00
Pawel Kojma 64511d30b6
Internals: Fix marking `AstVar`s as class members (#7070) 2026-02-13 07:45:13 -05:00
Geza Lore 3dd2b762e7
Fix scope tree in traces in hierarchical mode (#7042) 2026-02-12 20:54:03 -05:00
Wilson Snyder b84466ec10 Commentary: Changes update 2026-02-12 18:24:05 -05:00
Veripool API Bot b0fdbff6eb Verilog format 2026-02-12 18:23:56 -05:00
Wilson Snyder 13b1321985 Tests: Fix uvm_pkg_packer comment 2026-02-12 17:46:53 -05:00
Todd Strader fed41aba91
Fix UNUSED / UNDRIVEN for unused functions (#6967) 2026-02-12 11:01:14 -05:00
Yilou Wang 9b1b9a5b3b
Fix randc cyclic behavior broken with constraints (#7029) (#7035) 2026-02-12 10:58:04 -05:00
Igor Zaworski 446bec3d1a
Fix event triggering (#6932) 2026-02-11 10:35:59 -08:00
Yilou Wang e41436bd4a
Support inherited and nested pre/post_randomize callbacks (#7049) (#7053) 2026-02-11 09:33:57 -08:00
Yilou Wang 554fcef627
Fix rand_mode()/constraint_mode() when used as function arguments (#7051) (#7055) 2026-02-11 09:33:09 -08:00
Yilou Wang 996a4b6e1a
Fix constraint_mode()/rand_mode() in constructor being overwritten by init code (#7054) 2026-02-11 09:32:08 -08:00