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000-init-db
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Update 032 with some fixes found during interconnect fuzzing.
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2019-07-03 13:18:58 -07:00 |
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001-part-yaml
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…
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005-tilegrid
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Merge pull request #938 from antmicro/mmcme2-base-addr-fix
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2019-07-09 21:14:29 -07:00 |
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007-timing
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fuzzers: 007: fix Makefile targets definitions
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2019-07-02 19:04:10 +02:00 |
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010-clb-lutinit
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…
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011-clb-ffconfig
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Add support to zero db to support simple groups.
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2019-06-19 14:46:39 -07:00 |
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012-clb-n5ffmux
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…
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013-clb-ncy0
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…
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014-clb-ffsrcemux
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…
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015-clb-nffmux
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Ran format-py
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2019-07-10 16:15:28 +02:00 |
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016-clb-noutmux
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Ran format-py
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2019-07-10 16:15:28 +02:00 |
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017-clb-precyinit
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…
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018-clb-ram
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018-clb-ram: Increase specimen count
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2019-05-24 08:05:41 +02:00 |
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019-clb-ndi1mux
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Add support to zero db to support simple groups.
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2019-06-19 14:46:39 -07:00 |
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025-bram-config
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…
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026-bram-data
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…
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027-bram36-config
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…
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028-fifo-config
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…
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029-bram-fifo-config
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…
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030-iob
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030-iob: don't create liob segbits file for zynq
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2019-05-07 13:53:17 +02:00 |
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031-cmt-mmcm
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…
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032-cmt-pll
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Attempt to fix fuzzer error.
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2019-07-08 17:16:45 -07:00 |
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033-mon-xadc
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…
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034-cmt-pll-pips
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Fixes for zynq7 and PLL fuzzing.
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2019-07-03 13:19:03 -07:00 |
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035-iob-ilogic
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Expand ILOGIC fuzzer to document additional ISERDES bits.
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2019-07-08 17:00:06 -07:00 |
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036-iob-ologic
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…
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038-cfg
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038-cfg: Add fuzzer for the CFG tile
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2019-07-13 07:10:18 +02:00 |
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040-clk-hrow-config
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…
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041-clk-hrow-pips
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041-clk-hrow-pips: Balance todo list
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2019-06-19 11:11:20 +02:00 |
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042-clk-bufg-config
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…
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043-clk-rebuf-pips
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043-clk-rebuf-pips: increase the number of specimen
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2019-05-07 15:58:53 +02:00 |
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044-clk-bufg-pips
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044-clk-bufg-pips: Exclude CK_BUFG_(BOT|TOP)_R_CK_MUXED from todo list
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2019-06-25 18:52:00 +02:00 |
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045-hclk-cmt-pips
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045-hclk-cmt-pips: increase specimen count
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2019-05-13 10:17:35 +02:00 |
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046-clk-bufg-muxed-pips
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fuzzers: Add 046-clk-bufg-mixed-pips fuzzer
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2019-06-25 18:52:00 +02:00 |
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047-hclk-ioi-pips
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047-hclk-ioi-pips: Add targeted todo list routing to vivado script
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2019-07-19 08:19:00 +02:00 |
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048-int-piplist
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…
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049-int-imux-gfan
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…
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050-pip-seed
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050-pip-seed: Don't solve BYP_ALT|IMUX.LOGIC_OUTS_ bits
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2019-06-17 14:55:18 +02:00 |
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051-pip-imuxlout-bypalts
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…
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052-pip-clkin
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…
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053-pip-ctrlin
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053-pip-ctrlin: Fall back to todos bigger than specified number of lines
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2019-05-29 08:35:08 +02:00 |
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054-pip-fan-alt
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…
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055-pip-gnd
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…
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056-pip-rem
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056-pip-rem: Delete net and cell after unsuccessful routing attempt
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2019-05-10 11:14:10 +02:00 |
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057-pip-bi
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057-pip-bi: Increase try count limit
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2019-05-24 08:02:58 +02:00 |
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058-pip-hclk
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Add HCLK ppips.
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2019-06-11 14:58:15 -07:00 |
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059-pip-byp-bounce
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059-pip-byp-bounce: Add separate fuzzer for FAN_ALT.BYP_BOUNCE bits
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2019-06-05 19:26:07 +02:00 |
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060-bram-cascades
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…
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071-ppips
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Add HCLK ppips.
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2019-06-11 14:58:15 -07:00 |
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072-ordered_wires
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…
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073-get_counts
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…
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074-dump_all
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Avoid building full speed_model dict.
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2019-06-11 10:32:24 -07:00 |
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075-pins
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…
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100-dsp-mskpat
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…
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piplist
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…
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.gitignore
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…
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Makefile
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fuzzers: Add fuzzer for HCLK_IOI3 PIPs
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2019-07-19 08:19:00 +02:00 |
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clb.mk
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…
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clb_ext.mk
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Added a makefile which allows to fuzz features for both SLICEM and SLICEL but separate them during database merge.
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2019-07-10 15:06:58 +02:00 |
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fuzzer.mk
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…
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int_create_empty_db.sh
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…
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int_generate.py
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Fix problem with falsely ignored PIPs
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2019-06-27 08:01:01 +02:00 |
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int_loop.mk
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…
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int_loop.sh
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…
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int_loop_check.py
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int_loop_check.py: Fix output formatting
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2019-07-15 10:08:45 +02:00 |
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int_maketodo.py
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int_maketodo.py: Replace assertion with warning if PIP can't be balanced
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2019-06-19 11:11:40 +02:00 |
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pip_list.mk
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…
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pip_loop.mk
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053-pip-ctrlin: Fall back to todos bigger than specified number of lines
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2019-05-29 08:35:08 +02:00 |
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reseg.sh
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…
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run_fuzzer.py
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run_fuzzer.py: Adjust unit names output by free tool
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2019-05-09 09:33:22 +02:00 |
35ee0830a7