mirror of https://github.com/openXC7/prjxray.git
Fuzzers: add ologic fuzzer
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
This commit is contained in:
Karol Gugala
parent
ca45656e5f
commit
529e5a884a
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@ -0,0 +1,20 @@
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N := 40
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include ../fuzzer.mk
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database: build/segbits_xiob33.db
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build/segbits_xiob33.rdb: $(SPECIMENS_OK)
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${XRAY_SEGMATCH} -c 6 -o build/segbits_xiob33.rdb $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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build/segbits_xiob33.db: build/segbits_xiob33.rdb
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${XRAY_DBFIXUP} --db-root build --zero-db bits.dbf --seg-fn-in $^ --seg-fn-out $@
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${XRAY_MASKMERGE} build/mask_xiob33.db $$(find -name segdata_liob33.txt) $$(find -name segdata_riob33.txt)
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pushdb:
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${XRAY_MERGEDB} liob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} riob33 build/segbits_xiob33.db
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${XRAY_MERGEDB} mask_liob33 build/mask_xiob33.db
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${XRAY_MERGEDB} mask_riob33 build/mask_xiob33.db
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.PHONY: database pushdb
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@ -0,0 +1,3 @@
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31_92,IOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE
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30_35,IOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE
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@ -0,0 +1,100 @@
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#!/usr/bin/env python3
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from prjxray.segmaker import Segmaker
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from prjxray import verilog
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import json
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def handle_data_width(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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if d['DATA_RATE_OQ'] == 'DDR':
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return
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for opt in [2, 3, 4, 5, 6, 7, 8, 10, 14]:
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segmk.add_site_tag(
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d['site'], 'OSERDESE.DATA_WIDTH.{}'.format(opt),
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d['DATA_WIDTH'] == opt)
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def handle_data_rate(segmk, d):
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if 'DATA_WIDTH' not in d:
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return
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for opt in ['SDR', 'DDR']:
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segmk.add_site_tag(
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d['site'], 'OSERDESE.DATA_RATE.{}'.format(opt),
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verilog.unquote(d['DATA_RATE_OQ']) == opt)
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def main():
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print("Loading tags")
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segmk = Segmaker("design.bits")
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with open('params.jl', 'r') as f:
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design = json.load(f)
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for d in design:
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site = d['site']
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handle_data_width(segmk, d)
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handle_data_rate(segmk, d)
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if d['use_oserdese2']:
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if 'SRTYPE' in d:
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for opt in ['ASYNC', 'SYNC']:
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segmk.add_site_tag(
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site, 'OSERDESE.SRTYPE.{}'.format(opt),
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verilog.unquote(d['SRTYPE']) == opt)
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for opt in ['SDR', 'DDR']:
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segmk.add_site_tag(
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site, 'OSERDESE.DATA_RATE_OQ.{}'.format(opt),
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verilog.unquote(d['DATA_RATE_OQ']) == opt)
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for opt in ['BUF', 'SDR', 'DDR']:
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segmk.add_site_tag(
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site, 'OSERDESE.DATA_RATE_TQ.{}'.format(opt),
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verilog.unquote(d['DATA_RATE_TQ']) == opt)
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if d['oddr_mux_config'] != 'none':
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segmk.add_site_tag(site, 'OFF.ZINIT_Q', not d['QINIT'])
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for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
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segmk.add_site_tag(
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site, 'ODDR.DDR_CLK_EDGE.{}'.format(opt),
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verilog.unquote(d['ODDR_CLK_EDGE']) == opt)
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if d['tddr_mux_config'] != 'none':
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segmk.add_site_tag(site, 'TFF.ZINIT_Q', not d['TINIT'])
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# Note: edge settings seem to be ignored for TFF
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for opt in ['OPPOSITE_EDGE', 'SAME_EDGE']:
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segmk.add_site_tag(
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site, 'TDDR.DDR_CLK_EDGE.{}'.format(opt),
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verilog.unquote(d['TDDR_CLK_EDGE']) != opt)
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# all the bellow mux configs give 0 candidates
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# this is wierd, as they are set when DDR output is used
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# something's fishy here
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if d['oddr_mux_config'] == 'direct':
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segmk.add_site_tag(site, 'OMUXE2', 0)
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elif d['oddr_mux_config'] == 'none':
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segmk.add_site_tag(site, 'OMUXE2', 1)
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else:
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assert False, d['oddr_mux_config']
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if d['tddr_mux_config'] == 'direct':
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segmk.add_site_tag(site, 'TMUXE2', 0)
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elif d['tddr_mux_config'] == 'none':
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segmk.add_site_tag(site, 'TMUXE2', 1)
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else:
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assert False, d['tddr_mux_config']
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segmk.compile()
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segmk.write(allow_empty=True)
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if __name__ == "__main__":
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main()
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@ -0,0 +1,99 @@
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source "$::env(XRAY_DIR)/utils/utils.tcl"
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proc make_io_pin_sites {} {
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# get all possible IOB pins
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foreach pad [get_package_pins -filter "IS_GENERAL_PURPOSE == 1"] {
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set site [get_sites -of_objects $pad]
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if {[llength $site] == 0} {
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continue
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}
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if [string match IOB33* [get_property SITE_TYPE $site]] {
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dict append io_pin_sites $site $pad
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}
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}
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return $io_pin_sites
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}
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proc load_pin_lines {} {
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# IOB_X0Y103 clk input
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# IOB_X0Y129 do[0] output
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set fp [open "params.csv" r]
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gets $fp line
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set pin_lines {}
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for {gets $fp line} {$line != ""} {gets $fp line} {
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lappend pin_lines [split $line ","]
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}
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close $fp
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return $pin_lines
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}
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proc loc_pins {} {
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set pin_lines [load_pin_lines]
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set io_pin_sites [make_io_pin_sites]
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puts "Looping"
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for {set idx 0} {$idx < [llength $pin_lines]} {incr idx} {
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set line [lindex $pin_lines $idx]
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puts "$line"
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set site_str [lindex $line 1]
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set pin_str [lindex $line 2]
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set iostandard [lindex $line 3]
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set drive [lindex $line 4]
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set slew [lindex $line 5]
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set pulltype [lindex $line 6]
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# Have: site
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# Want: pin for site
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set site [get_sites $site_str]
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set pad_bel [get_bels -of_objects $site -filter {TYPE =~ PAD && NAME =~ IOB_*}]
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# set port [get_ports -of_objects $site]
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set port [get_ports $pin_str]
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set tile [get_tiles -of_objects $site]
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set pin [dict get $io_pin_sites $site]
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set props {}
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#lappend props PACKAGE_PIN $pin
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lappend props IOSTANDARD $iostandard
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lappend props PULLTYPE $pulltype
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if {$drive != "None"} {
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lappend props DRIVE $drive
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}
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if {$slew != "None"} {
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lappend props SLEW $slew
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}
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puts $props
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set_property -dict "$props" $port
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}
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}
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proc run {} {
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create_project -force -part $::env(XRAY_PART) design design
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read_verilog top.v
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synth_design -top top
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loc_pins
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set_property CFGBVS VCCO [current_design]
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set_property CONFIG_VOLTAGE 3.3 [current_design]
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set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
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set_property IS_ENABLED 0 [get_drc_checks {REQP-79}]
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write_checkpoint -force design_pre_place.dcp
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place_design
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route_design
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write_checkpoint -force design.dcp
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write_bitstream -force design.bit
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}
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run
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@ -0,0 +1,323 @@
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import json
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import io
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import os
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import random
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random.seed(int(os.getenv("SEED"), 16))
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from prjxray import util
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from prjxray import lut_maker
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from prjxray import verilog
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from prjxray.db import Database
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def gen_sites():
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'''
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IOB33S: main IOB of a diff pair
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IOB33M: secondary IOB of a diff pair
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IOB33: not a diff pair. Relatively rare (at least in ROI...2 of them?)
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Focus on IOB33S to start
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'''
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db = Database(util.get_db_root())
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grid = db.grid()
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for tile_name in sorted(grid.tiles()):
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loc = grid.loc_of_tilename(tile_name)
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gridinfo = grid.gridinfo_at_loc(loc)
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for site_name, site_type in gridinfo.sites.items():
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if site_type in ['IOB33S', 'IOB33M']:
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yield tile_name, site_name
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def write_params(params):
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pinstr = 'tile,site,pin,iostandard,drive,slew\n'
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for vals in params:
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pinstr += ','.join(map(str, vals)) + '\n'
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open('params.csv', 'w').write(pinstr)
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def use_oserdese2(p, luts, connects):
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p['oddr_mux_config'] = 'none'
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p['tddr_mux_config'] = 'none'
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p['DATA_RATE_OQ'] = verilog.quote(random.choice((
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'SDR',
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'DDR',
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)))
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p['DATA_RATE_TQ'] = verilog.quote(random.choice((
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'BUF',
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'SDR',
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'DDR',
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)))
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if verilog.unquote(p['DATA_RATE_OQ']) == 'SDR':
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data_widths = [2, 3, 4, 5, 6, 7, 8]
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else:
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data_widths = [4, 6, 8]
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p['DATA_WIDTH'] = random.choice(data_widths)
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if p['DATA_WIDTH'] == 4 and verilog.unquote(
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p['DATA_RATE_OQ']) == 'DDR' and verilog.unquote(
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p['DATA_RATE_TQ']) == 'DDR':
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tristate_width = 4
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else:
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tristate_width = 1
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p['SERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
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p['TRISTATE_WIDTH'] = tristate_width
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p['OSERDES_MODE'] = verilog.quote(random.choice(('MASTER', 'SLAVE')))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
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OSERDESE2 #(
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.SERDES_MODE({OSERDES_MODE}),
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.DATA_RATE_TQ({DATA_RATE_TQ}),
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.DATA_RATE_OQ({DATA_RATE_OQ}),
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.DATA_WIDTH({DATA_WIDTH}),
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.TRISTATE_WIDTH({TRISTATE_WIDTH})
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) oserdese2_{site} (
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.OQ({owire}),
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.TFB(tfb_{site}),
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.TQ({twire}),
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.CLK({clknet}),
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.CLKDIV({clkdivnet}),
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.D1({d1net}),
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.D2({d2net}),
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.D3({d3net}),
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.D4({d4net}),
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.D5({d5net}),
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.D6({d6net}),
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.D7({d7net}),
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.D8({d8net}),
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.OCE({ocenet}),
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.RST({rstnet}),
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.T1({t1net}),
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.T2({t2net}),
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.T3({t3net}),
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.T4({t4net}),
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.TCE({tcenet})
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);'''.format(
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clknet=luts.get_next_output_net(),
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clkdivnet=luts.get_next_output_net(),
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rstnet=luts.get_next_output_net(),
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d1net=luts.get_next_output_net(),
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d2net=luts.get_next_output_net(),
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d3net=luts.get_next_output_net(),
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d4net=luts.get_next_output_net(),
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d5net=luts.get_next_output_net(),
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d6net=luts.get_next_output_net(),
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d7net=luts.get_next_output_net(),
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d8net=luts.get_next_output_net(),
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t1net=luts.get_next_output_net(),
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t2net=luts.get_next_output_net(),
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t3net=luts.get_next_output_net(),
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t4net=luts.get_next_output_net(),
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tcenet=luts.get_next_output_net(),
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ocenet=luts.get_next_output_net(),
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ofb_wire=luts.get_next_input_net(),
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**p),
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file=connects)
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def use_direct_and_oddr(p, luts, connects):
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p['oddr_mux_config'] = random.choice((
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'direct',
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'none',
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))
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p['tddr_mux_config'] = random.choice((
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'direct',
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'none',
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))
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# toddr and oddr share the same clk
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clknet = luts.get_next_output_net()
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if p['tddr_mux_config'] != 'none':
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p['TINIT'] = random.randint(0, 1)
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p['TSRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
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p['TDDR_CLK_EDGE'] = verilog.quote('OPPOSITE_EDGE')
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# Note: it seems that CLK_EDGE setting is ignored for TDDR
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p['TDDR_CLK_EDGE'] = verilog.quote(
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random.choice(('OPPOSITE_EDGE', 'SAME_EDGE')))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
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ODDR #(
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.INIT({TINIT}),
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.SRTYPE({TSRTYPE}),
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.DDR_CLK_EDGE({TDDR_CLK_EDGE})
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) toddr_{site} (
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.C({cnet}),
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.D1({d1net}),
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.D2({d2net}),
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.CE({cenet}),
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.Q(tddr_d_{site})
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);
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'''.format(
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cnet=clknet,
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d1net=luts.get_next_output_net(),
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d2net=luts.get_next_output_net(),
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cenet=luts.get_next_output_net(),
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**p),
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file=connects)
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if p['tddr_mux_config'] == 'direct':
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print(
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'''
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assign {twire} = tddr_d_{site};'''.format(**p, ),
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file=connects)
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elif p['tddr_mux_config'] == 'none':
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pass
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else:
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assert False, p['tddr_mux_config']
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if p['oddr_mux_config'] != 'none':
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p['QINIT'] = random.randint(0, 1)
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p['SRTYPE'] = verilog.quote(random.choice(('SYNC', 'ASYNC')))
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p['ODDR_CLK_EDGE'] = verilog.quote(
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random.choice((
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'OPPOSITE_EDGE',
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'SAME_EDGE',
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)))
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print(
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'''
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(* KEEP, DONT_TOUCH, LOC = "{ologic_loc}" *)
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ODDR #(
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.INIT({QINIT}),
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.SRTYPE({SRTYPE}),
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.DDR_CLK_EDGE({ODDR_CLK_EDGE})
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) oddr_{site} (
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.C({cnet}),
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.D1({d1net}),
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.D2({d2net}),
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.CE({cenet}),
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.Q(oddr_d_{site})
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);
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'''.format(
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cnet=clknet,
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d1net=luts.get_next_output_net(),
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d2net=luts.get_next_output_net(),
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cenet=luts.get_next_output_net(),
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**p),
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file=connects)
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if p['oddr_mux_config'] == 'direct':
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print(
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'''
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assign {owire} = oddr_d_{site};'''.format(**p, ),
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file=connects)
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elif p['oddr_mux_config'] == 'none':
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pass
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else:
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assert False, p['oddr_mux_config']
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def run():
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iostandards = [
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'LVCMOS12', 'LVCMOS15', 'LVCMOS18', 'LVCMOS25', 'LVCMOS33', 'LVTTL'
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]
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iostandard = random.choice(iostandards)
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if iostandard in ['LVTTL', 'LVCMOS18']:
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drives = [4, 8, 12, 16, 24]
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elif iostandard == 'LVCMOS12':
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drives = [4, 8, 12]
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else:
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drives = [4, 8, 12, 16]
|
||||
|
||||
slews = ['FAST', 'SLOW']
|
||||
pulls = ["NONE", "KEEPER", "PULLDOWN", "PULLUP"]
|
||||
|
||||
luts = lut_maker.LutMaker()
|
||||
|
||||
connects = io.StringIO()
|
||||
|
||||
tile_params = []
|
||||
params = []
|
||||
for idx, (tile, site) in enumerate(gen_sites()):
|
||||
if idx == 0:
|
||||
continue
|
||||
|
||||
p = {}
|
||||
p['tile'] = tile
|
||||
p['site'] = site
|
||||
p['ilogic_loc'] = site.replace('IOB', 'ILOGIC')
|
||||
p['ologic_loc'] = site.replace('IOB', 'OLOGIC')
|
||||
p['IOSTANDARD'] = verilog.quote(iostandard)
|
||||
p['PULLTYPE'] = verilog.quote(random.choice(pulls))
|
||||
p['DRIVE'] = random.choice(drives)
|
||||
p['SLEW'] = verilog.quote(random.choice(slews))
|
||||
|
||||
p['pad_wire'] = 'dio[{}]'.format(idx - 1)
|
||||
p['owire'] = 'do_buf[{}]'.format(idx - 1)
|
||||
p['iwire'] = 'di_buf[{}]'.format(idx - 1)
|
||||
p['twire'] = 't[{}]'.format(idx - 1)
|
||||
|
||||
params.append(p)
|
||||
tile_params.append(
|
||||
(
|
||||
tile, site, p['pad_wire'], iostandard, p['DRIVE'],
|
||||
verilog.unquote(p['SLEW']) if p['SLEW'] else None,
|
||||
verilog.unquote(p['PULLTYPE'])))
|
||||
|
||||
write_params(tile_params)
|
||||
|
||||
print(
|
||||
'''
|
||||
`define N_DI {n_di}
|
||||
|
||||
module top(input clk, inout wire [`N_DI-1:0] dio);
|
||||
wire [`N_DI-1:0] di_buf;
|
||||
wire [`N_DI-1:0] do_buf;
|
||||
wire [`N_DI-1:0] t;
|
||||
'''.format(n_di=idx))
|
||||
|
||||
# Always output a LUT6 to make placer happy.
|
||||
print(
|
||||
'''
|
||||
(* KEEP, DONT_TOUCH *)
|
||||
LUT6 dummy_lut();
|
||||
''')
|
||||
|
||||
for p in params:
|
||||
print(
|
||||
'''
|
||||
wire oddr_d_{site};
|
||||
|
||||
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
|
||||
IOBUF #(
|
||||
.IOSTANDARD({IOSTANDARD})
|
||||
) obuf_{site} (
|
||||
.IO({pad_wire}),
|
||||
.I({owire}),
|
||||
.O({iwire}),
|
||||
.T({twire})
|
||||
);
|
||||
'''.format(**p),
|
||||
file=connects)
|
||||
|
||||
p['use_oserdese2'] = random.randint(0, 1)
|
||||
if p['use_oserdese2']:
|
||||
use_oserdese2(p, luts, connects)
|
||||
else:
|
||||
use_direct_and_oddr(p, luts, connects)
|
||||
|
||||
for l in luts.create_wires_and_luts():
|
||||
print(l)
|
||||
|
||||
print(connects.getvalue())
|
||||
|
||||
print("endmodule")
|
||||
|
||||
with open('params.jl', 'w') as f:
|
||||
json.dump(params, f, indent=2)
|
||||
|
||||
|
||||
if __name__ == '__main__':
|
||||
run()
|
||||
|
|
@ -75,6 +75,7 @@ $(eval $(call fuzzer,028-fifo-config,005-tilegrid))
|
|||
$(eval $(call fuzzer,029-bram-fifo-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,030-iob,005-tilegrid))
|
||||
$(eval $(call fuzzer,035-iob-ilogic,005-tilegrid))
|
||||
$(eval $(call fuzzer,036-iob-ologic,005-tilegrid))
|
||||
$(eval $(call fuzzer,040-clk-hrow-config,005-tilegrid))
|
||||
$(eval $(call fuzzer,041-clk-hrow-pips,005-tilegrid))
|
||||
# 042 fuzzer is unstable, issue #657
|
||||
|
|
|
|||
Loading…
Reference in New Issue