31cfa88344
generate both xc7010 and xc7020 parts
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 11:26:55 +01:00
b211908e26
zynq: fuzzers: Remove Zynq specific workarounds
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 10:21:38 +01:00
fb26896dcb
zynq: Allow LIOB baseaddr
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-27 10:21:38 +01:00
13ba74194a
zynq: Add BRKH_INT_PSS tile type to fix assertion
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2020-01-27 10:20:22 +01:00
4849f49724
005-tilegrid: added comment on EXCLUDE_ROI env variable
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
cb9944d392
005-tilegrid: use variable for dependencies
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
127412b5b9
fix wrong location of tilegrid and yaml
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e44027bcaf
Move all part-specific files to dedicated directory
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
c5a33cb161
005-tilegrid: further increasing to 6 number of specimens for mmcm
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
e8a2777a17
005-tilegrid: reduce number of specimens
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Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
5c829daa8c
005-tilegrid: fixed some over-specific settings in generate_full
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Also added specimens to make some rquired fuzzers find all necessary
features
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
93d1ae82f7
Enable the generation of extra part-dependents files
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This change affects the extra-db target, by adding also the generation
of other part-dependent files, such as tilegrid, tileconn, and others.
Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>
2020-01-24 10:13:33 +01:00
cce638930c
Add clock_region to tilegrid.json for constructing clock networks.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-12-14 22:28:22 -08:00
97699e4e93
Add HCLK_[LR]_BOT_UTURN aliases.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-23 15:30:27 -07:00
c0b8aef3a9
Add pin functions to tilegrid.
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- Add support to emit PUDC_B pullup if unused (for A7 and Z7 fabrics).
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-10-14 16:38:02 -07:00
4efb540d96
Add stepdown feature to HCLK_IOI.
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- Also narrow HCLK_IOI tilegrid size to avoid coupling into [RL]IOI3.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-30 16:03:25 -07:00
5de6e16b29
005-tilegrid: Add alias for IOI3_SING tiles
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-07-26 13:34:44 +02:00
05ef773e60
Merge pull request #938 from antmicro/mmcme2-base-addr-fix
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fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
2019-07-09 21:14:29 -07:00
b989c2fc05
fuzzers: tilegrid: mmcme: LOC mmcme2_adv instances
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Signed-off-by: Karol Gugala <kgugala@antmicro.com>
2019-07-09 18:42:04 +02:00
f92fb52576
Merge branch 'master' into add_pll_interconnect_fuzzer
2019-07-08 11:22:49 -07:00
b77c47b155
Fixes for zynq7 and PLL fuzzing.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:19:03 -07:00
30648d554a
Complete initial PLL fuzzer.
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This solves for all unknown bits, but results in a large "IN_USE"
feature for apparently constant bits.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-07-03 13:18:58 -07:00
e096d9c172
005-tilegrid: Add HCLK_IOI base addresses calculation
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-07-01 08:58:45 +02:00
86164fdc18
005-tilegrid: propagate IOI SING and Y9 tiles
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 12:12:37 +02:00
9fb26b6915
005-tilegrid: calculate IOI base address
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-06-25 11:32:32 +02:00
369362f8c8
005-tilegrid: add CFG_CENTER_MID tile base address calculation
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Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
2019-05-31 09:40:40 +02:00
66c7c4c3ab
Add fuzzers for HCLK_CMT tiles.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-15 18:43:21 -07:00
c2df5c97eb
Working complete HROW pip fuzzer.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-14 20:05:27 -07:00
1307e11397
IOB_SING solution via segbit aliases.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-03-01 17:02:18 -08:00
095d8c86ff
Fix missing IOB base address.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-13 22:47:29 -08:00
51100d0ced
Merge pull request #648 from litghost/rework_tilegrid
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Sort tiles and revamp gen_fuzz_states to be more efficient.
2019-02-13 18:42:06 -08:00
7c467920e6
Convert BRAM block tilegrid fuzzer to use first RAMB18E1.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-13 18:25:09 -08:00
ab7347877f
Run make format.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-13 18:08:23 -08:00
7e4e4b19fc
Sort tiles and revamp gen_fuzz_states to be more efficient.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-13 17:59:37 -08:00
457c0cde6f
Make generic generate_top for tilegrid.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 16:43:02 -08:00
73a5c04544
Add _ACTIVE bits to HROW bits.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 16:33:59 -08:00
9ccc58b077
Run make format.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 15:18:25 -08:00
88b2fc6d35
Fix 043 to document remaining bits.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 15:15:46 -08:00
5bebeb6c0d
Add CLK_BUFG to tilegrid.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 15:15:34 -08:00
f29fe77ea9
Add initial REBUF pips.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-12 15:15:34 -08:00
1011a90769
Run make format.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-08 14:28:54 -08:00
00d9e1f314
Add CLK_HROW config fuzzer, and adjust tilegrid definition.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-08 14:23:39 -08:00
5e9cb60917
Add base addresses for CLK_HROW tiles. Word offset may be wrong.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-08 13:00:54 -08:00
b04598da26
Solve orphan INT columns in Kintex7.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-07 15:01:09 -08:00
bcd41b8d08
Add XADC INT and ICAP INT fuzzers to solve 2 of 4 missing INT columns.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-02-07 09:36:02 -08:00
0d0116b6eb
Makes minor documentation change.
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Signed-off-by: Paul Schulz <paul@mawsonlakes.org>
2019-02-03 00:59:43 +10:30
d964d8a363
Makes minor formatting chamges to documentation
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Signed-off-by: Paul Schulz <paul@mawsonlakes.org>
2019-02-03 00:46:45 +10:30
ff3839f2b1
Remove some of the __future__.]
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-28 12:54:36 -08:00
2b223ac86c
Run make format.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-28 11:32:16 -08:00
bf8fd49ba4
Remove remaining usage of height, as words is the key.
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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
2019-01-28 11:31:44 -08:00
Alessandro Comodi
Tomasz Michalak
Keith Rothman
Karol Gugala
Paul Schulz