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Make generic generate_top for tilegrid. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-12 16:43:02 -08:00
parent 73a5c04544
commit 457c0cde6f
8 changed files with 24 additions and 123 deletions
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18
fuzzers/005-tilegrid/bram_int/generate.tcl
View File

@ -1,19 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

18
fuzzers/005-tilegrid/cfg_int/generate.tcl
View File

@ -1,19 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

20
fuzzers/005-tilegrid/clk_bufg/generate.tcl
View File

@ -1,21 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
#set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

20
fuzzers/005-tilegrid/clk_hrow/generate.tcl
View File

@ -1,21 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
#set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk]
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

18
fuzzers/005-tilegrid/dsp/generate.tcl
View File

@ -1,19 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

18
fuzzers/005-tilegrid/fifo_int/generate.tcl
View File

@ -1,19 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

18
fuzzers/005-tilegrid/monitor_int/generate.tcl
View File

@ -1,19 +1,3 @@
source "$::env(XRAY_DIR)/utils/utils.tcl"
proc run {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}
run
generate_top

17
utils/utils.tcl
View File

@ -131,3 +131,20 @@ proc write_pip_txtdata {filename} {
}
close $fp
}
# Generic non-ROI'd generate.tcl template
proc generate_top {} {
create_project -force -part $::env(XRAY_PART) design design
read_verilog top.v
synth_design -top top
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design]
place_design
route_design
write_checkpoint -force design.dcp
write_bitstream -force design.bit
}