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Run make format. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-02-12 15:18:25 -08:00
parent e7d32dadb4
commit 9ccc58b077
5 changed files with 51 additions and 40 deletions
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16
fuzzers/005-tilegrid/generate_full.py
View File

@ -210,6 +210,7 @@ def propagate_INT_bits_in_column(database, tiles_by_grid):
tile_name = next_tile
tile = database[tile_name]
def propagate_rebuf(database, tiles_by_grid):
""" Writing a fuzzer for the CLK_BUFG_REBUF tiles is hard, so propigate from CLK_HROW tiles.
@ -225,16 +226,21 @@ def propagate_rebuf(database, tiles_by_grid):
continue
rebuf_below = tiles_by_grid[(tile['grid_x'], tile['grid_y'] - 12)]
assert database[rebuf_below]['type'] == 'CLK_BUFG_REBUF', database[rebuf_below]['type']
assert database[rebuf_below]['type'] == 'CLK_BUFG_REBUF', database[
rebuf_below]['type']
rebuf_above = tiles_by_grid[(tile['grid_x'], tile['grid_y'] + 13)]
assert database[rebuf_above]['type'] == 'CLK_BUFG_REBUF', database[rebuf_below]['type']
assert database[rebuf_above]['type'] == 'CLK_BUFG_REBUF', database[
rebuf_below]['type']
assert database[tile_name]['bits']['CLB_IO_CLK']['offset'] == 47, database[tile_name]['bits']['CLB_IO_CLK']
database[rebuf_below]['bits'] = copy.deepcopy(database[tile_name]['bits'])
assert database[tile_name]['bits']['CLB_IO_CLK'][
'offset'] == 47, database[tile_name]['bits']['CLB_IO_CLK']
database[rebuf_below]['bits'] = copy.deepcopy(
database[tile_name]['bits'])
database[rebuf_below]['bits']['CLB_IO_CLK']['offset'] = 73
database[rebuf_below]['bits']['CLB_IO_CLK']['words'] = 4
database[rebuf_above]['bits'] = copy.deepcopy(database[tile_name]['bits'])
database[rebuf_above]['bits'] = copy.deepcopy(
database[tile_name]['bits'])
database[rebuf_above]['bits']['CLB_IO_CLK']['offset'] = 24
database[rebuf_above]['bits']['CLB_IO_CLK']['words'] = 4

32
fuzzers/042-clk-bufg-config/generate.py
View File

@ -25,39 +25,33 @@ def main():
'INIT_OUT',
'IS_IGNORE0_INVERTED',
'IS_IGNORE1_INVERTED',
):
):
segmk.add_site_tag(
row['site'], '{}.{}'.format(base_name, param), row[param])
if row['connect0'] and row['connect1']:
for param in (
'PRESELECT_I0',
):
for param in ('PRESELECT_I0', ):
segmk.add_site_tag(
row['site'], '{}.Z{}'.format(base_name, param), 1 ^ row[param])
row['site'], '{}.Z{}'.format(base_name, param),
1 ^ row[param])
for param in (
'PRESELECT_I1',
):
for param in ('PRESELECT_I1', ):
segmk.add_site_tag(
row['site'], '{}.{}'.format(base_name, param), row[param])
if row['connect0']:
for param, tag in (
('IS_CE0_INVERTED', 'ZINV_CE0'),
('IS_S0_INVERTED', 'ZINV_S0')
):
for param, tag in (('IS_CE0_INVERTED', 'ZINV_CE0'),
('IS_S0_INVERTED', 'ZINV_S0')):
segmk.add_site_tag(
row['site'], '{}.{}'.format(base_name, tag), 1 ^ row[param])
row['site'], '{}.{}'.format(base_name, tag),
1 ^ row[param])
if row['connect1']:
for param, tag in (
('IS_CE1_INVERTED', 'ZINV_CE1'),
('IS_S1_INVERTED', 'ZINV_S1')
):
for param, tag in (('IS_CE1_INVERTED', 'ZINV_CE1'),
('IS_S1_INVERTED', 'ZINV_S1')):
segmk.add_site_tag(
row['site'], '{}.{}'.format(base_name, tag), 1 ^ row[param])
row['site'], '{}.{}'.format(base_name, tag),
1 ^ row[param])
segmk.compile()
segmk.write()

2
fuzzers/042-clk-bufg-config/top.py
View File

@ -87,8 +87,6 @@ module top();
.S1(s1_{site})
""".format(site=site)
print(
'''
wire ce0_{site};

33
fuzzers/043-clk-rebuf-pips/generate.py
View File

@ -9,11 +9,13 @@ REBUF_GCLK = re.compile('^CLK_BUFG_REBUF_R_CK_GCLK([0-9]+)_BOT$')
GCLKS = 32
def gclk_of_wire(wire):
m = REBUF_GCLK.match(wire)
assert m, wire
return int(m.group(1))
class ClockColumn(object):
def __init__(self, db_root):
db = Database(db_root)
@ -32,12 +34,15 @@ class ClockColumn(object):
tiles_in_gclk_columns.append((loc.grid_y, tile))
_, self.tiles_in_gclk_columns = zip(*sorted(tiles_in_gclk_columns, key=lambda x: x[0]))
_, self.tiles_in_gclk_columns = zip(
*sorted(tiles_in_gclk_columns, key=lambda x: x[0]))
# Initially all GCLK lines are idle. GCLK lines only exist between
# Initially all GCLK lines are idle. GCLK lines only exist between
#CLK_BUFG_REBUF tiles, hence len-1.
for gclk in range(GCLKS):
self.gclk_columns[gclk] = [False for _ in range(len(self.tiles_in_gclk_columns)-1)]
self.gclk_columns[gclk] = [
False for _ in range(len(self.tiles_in_gclk_columns) - 1)
]
def enable_rebuf(self, tile, wire):
# Find which REBUF is being activated.
@ -47,7 +52,7 @@ class ClockColumn(object):
gclk = gclk_of_wire(wire)
self.gclk_columns[gclk][rebuf_idx] = True
self.gclk_columns[gclk][rebuf_idx-1] = True
self.gclk_columns[gclk][rebuf_idx - 1] = True
def yield_rebuf_state(self):
""" Yields tile_name, gclk, bool if active above tile, bool if active below tile """
@ -57,7 +62,7 @@ class ClockColumn(object):
active_above = False
if idx > 0:
active_below = self.gclk_columns[gclk][idx-1]
active_below = self.gclk_columns[gclk][idx - 1]
if idx < len(self.gclk_columns[gclk]):
active_above = self.gclk_columns[gclk][idx]
@ -79,7 +84,8 @@ def main():
if 'CLK_BUFG_REBUF' not in line:
continue
parts = line.replace('{', '').replace('}','').strip().replace('\t', ' ').split(' ')
parts = line.replace('{', '').replace('}', '').strip().replace(
'\t', ' ').split(' ')
dst = parts[0]
pip = parts[3]
@ -104,14 +110,19 @@ def main():
b_to_a = wire_a != dst
a_to_b = not b_to_a
segmk.add_tile_tag(tile_from_pip, '{}.{}'.format(wire_a, wire_b), b_to_a)
segmk.add_tile_tag(tile_from_pip, '{}.{}'.format(wire_b, wire_a), a_to_b)
segmk.add_tile_tag(
tile_from_pip, '{}.{}'.format(wire_a, wire_b), b_to_a)
segmk.add_tile_tag(
tile_from_pip, '{}.{}'.format(wire_b, wire_a), a_to_b)
clock_column.enable_rebuf(tile_from_pip, wire_a)
for tile, gclk, active_below, active_above in clock_column.yield_rebuf_state():
segmk.add_tile_tag(tile, 'GCLK{}_ENABLE_ABOVE'.format(gclk), active_above)
segmk.add_tile_tag(tile, 'GCLK{}_ENABLE_BELOW'.format(gclk), active_below)
for tile, gclk, active_below, active_above in clock_column.yield_rebuf_state(
):
segmk.add_tile_tag(
tile, 'GCLK{}_ENABLE_ABOVE'.format(gclk), active_above)
segmk.add_tile_tag(
tile, 'GCLK{}_ENABLE_BELOW'.format(gclk), active_below)
segmk.compile()
segmk.write(allow_empty=True)

8
fuzzers/043-clk-rebuf-pips/top.py
View File

@ -52,6 +52,7 @@ def gen_bufhce_sites():
if sites:
yield tile_name, set(sites)
def main():
print('''
module top();
@ -78,20 +79,21 @@ module top();
opts = []
for count in range(len(bufhce_sites)):
for opt in itertools.combinations(bufhce_sites, count+1):
for opt in itertools.combinations(bufhce_sites, count + 1):
opts.append(opt)
for gclk in gclks:
for tile_name, sites in random.choice(opts):
for site in sorted(sites):
print("""
print(
"""
(* KEEP, DONT_TOUCH, LOC = "{site}" *)
BUFHCE buf_{site} (
.I({wire_name})
);""".format(
site=site,
wire_name=gclk,
))
))
sites.remove(site)
break