Cleanup
This commit is contained in:
Miodrag Milanovic
parent
74265fd1b8
commit
b8c59f9f80
800
gatemate/die.py
800
gatemate/die.py
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@ -247,6 +247,269 @@ class TileInfo:
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tile_y : int
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prim_index : int
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RAM_HALF_PINS = [
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Pin("CLKA[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("CLKA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ENA[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ENA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("GLWEA[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("GLWEA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("CLKB[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("CLKB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ENB[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ENB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("GLWEB[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("GLWEB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[7]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[8]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[9]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[10]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[11]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[12]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[13]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[14]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[15]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[16]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[17]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[18]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[19]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[7]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[8]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[9]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[10]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[11]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[12]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[13]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[14]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[15]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[16]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[17]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[18]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEB[19]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[7]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[8]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[9]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[10]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[11]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[12]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[13]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[14]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRA0[15]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[1]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[2]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[3]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[4]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[5]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[6]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[7]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[8]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[9]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[10]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[11]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[12]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[13]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[14]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRA0X[15]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[7]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[8]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[9]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[10]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[11]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[12]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[13]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[14]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ADDRB0[15]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[1]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[2]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[3]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[4]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[5]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[6]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[7]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[8]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[9]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[10]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[11]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[12]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[13]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[14]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ADDRB0X[15]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[7]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[8]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[9]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[10]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[11]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[12]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[13]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[14]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[15]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[16]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[17]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[18]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIA[19]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[7]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[8]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[9]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[10]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[11]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[12]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[13]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[14]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[15]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[16]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[17]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[18]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DIB[19]", PinType.INPUT,"RAM_WIRE", True),
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Pin("DOA[0]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[0]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[1]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[1]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[2]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[2]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[3]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[3]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[4]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[4]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[5]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[5]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[6]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[6]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[7]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[7]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[8]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[8]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[9]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[9]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[10]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[10]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[11]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[11]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[12]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[12]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[13]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[13]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[14]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[14]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[15]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[15]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[16]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[16]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[17]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[17]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOA[18]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[18]", PinType.OUTPUT,"RAM_WIRE, True),
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Pin("DOA[19]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOAX[19]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[0]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[0]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[1]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[1]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[2]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[2]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[3]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[3]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[4]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[4]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[5]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[5]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[6]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[6]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[7]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[7]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[8]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[8]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[9]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[9]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[10]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[10]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[11]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[11]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[12]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[12]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[13]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[13]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[14]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[14]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[15]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[15]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[16]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[16]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[17]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[17]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[18]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[18]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("DOB[19]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("DOBX[19]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("ECC1B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("ECC1B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("ECC1B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("ECC1B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("ECC2B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("ECC2B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("ECC2B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True),
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#Pin("ECC2B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True),
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Pin("CLOCK1", PinType.INPUT,"RAM_WIRE", True),
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Pin("CLOCK2", PinType.INPUT,"RAM_WIRE", True),
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Pin("CLOCK3", PinType.INPUT,"RAM_WIRE", True),
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Pin("CLOCK4", PinType.INPUT,"RAM_WIRE", True),
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]
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PRIMITIVES_PINS = {
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"CPE_LT_U": [
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Pin("IN1" ,PinType.INPUT, "CPE_WIRE", True),
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@ -1072,528 +1335,8 @@ PRIMITIVES_PINS = {
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Pin("CLOCK3", PinType.INPUT,"RAM_WIRE"),
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Pin("CLOCK4", PinType.INPUT,"RAM_WIRE"),
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],
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"RAM_HALF_U" : [
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Pin("CLKA[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("CLKA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ENA[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ENA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("GLWEA[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("GLWEA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("CLKB[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("CLKB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("ENB[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("ENB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("GLWEB[0]", PinType.INPUT,"RAM_WIRE", True),
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#Pin("GLWEB[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[0]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[1]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[2]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[3]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[4]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[5]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[6]", PinType.INPUT,"RAM_WIRE", True),
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Pin("WEA[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("WEB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("ADDRA0[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("ADDRB0[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DIA[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DIB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DOA[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[18]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[18]", PinType.OUTPUT,"RAM_WIRE, True),
|
||||
Pin("DOA[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DOB[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[18]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[18]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("ECC1B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC1B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("ECC1B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC1B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("ECC2B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC2B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("ECC2B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC2B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("CLOCK1", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("CLOCK2", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("CLOCK3", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("CLOCK4", PinType.INPUT,"RAM_WIRE", True),
|
||||
],
|
||||
"RAM_HALF_L" : [
|
||||
Pin("CLKA[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("CLKA[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ENA[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ENA[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("GLWEA[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("GLWEA[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("CLKB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("CLKB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ENB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ENB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("GLWEB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("GLWEB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("WEA[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEA[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("WEB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("WEB[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("ADDRA0[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRA0[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRA0X[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("ADDRB0[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("ADDRB0[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
#Pin("ADDRB0X[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DIA[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIA[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DIB[0]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[1]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[2]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[3]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[4]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[5]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[6]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[7]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[8]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[9]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[10]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[11]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[12]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[13]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[14]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[15]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[16]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[17]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[18]", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("DIB[19]", PinType.INPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DOA[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOA[18]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[18]", PinType.OUTPUT,"RAM_WIRE, True),
|
||||
Pin("DOA[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOAX[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("DOB[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[1]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[3]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[4]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[5]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[6]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[7]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[8]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[9]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[10]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[11]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[12]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[13]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[14]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[15]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[16]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[17]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[18]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[18]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("DOB[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("DOBX[19]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("ECC1B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC1B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("ECC1B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC1B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("ECC2B_ERRA[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC2B_ERRA[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
Pin("ECC2B_ERRB[0]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
#Pin("ECC2B_ERRB[2]", PinType.OUTPUT,"RAM_WIRE", True),
|
||||
|
||||
Pin("CLOCK1", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("CLOCK2", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("CLOCK3", PinType.INPUT,"RAM_WIRE", True),
|
||||
Pin("CLOCK4", PinType.INPUT,"RAM_WIRE", True),
|
||||
],
|
||||
"RAM_HALF_U" : RAM_HALF_PINS,
|
||||
"RAM_HALF_L" : RAM_HALF_PINS,
|
||||
"SERDES" : [
|
||||
Pin("TX_DETECT_RX_I", PinType.INPUT,"SERDES_WIRE"),
|
||||
Pin("PLL_RESET_I", PinType.INPUT,"SERDES_WIRE"),
|
||||
|
|
@ -4330,16 +4073,7 @@ class Die:
|
|||
def create_ram(self, x, y):
|
||||
self.create_ram_io_conn("RAM", "RAM", x, y)
|
||||
# No actuall need for connections to RAMI/O
|
||||
# for halfs, they create conflicts and we
|
||||
# later anyway merge to full RAM
|
||||
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, y, "RAM.CLOCK1")
|
||||
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, y, "RAM.CLOCK2")
|
||||
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB2", x, y, "RAM.CLOCK3")
|
||||
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB3", x, y, "RAM.CLOCK4")
|
||||
|
||||
def create_ram_l(self, x, y):
|
||||
# No actuall need for connections to RAMI/O
|
||||
# for halfs, they create conflicts and we
|
||||
# for halfs, they create conflicts and we
|
||||
# later anyway merge to full RAM
|
||||
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB0", x, y, "RAM.CLOCK1")
|
||||
self.create_conn(PLL_X_POS, PLL_Y_POS, "GLBOUT.GLB1", x, y, "RAM.CLOCK2")
|
||||
|
|
@ -4361,8 +4095,6 @@ class Die:
|
|||
self.create_io(x,y)
|
||||
if is_ram_u(x,y):
|
||||
self.create_ram(x,y)
|
||||
if is_ram_l(x,y):
|
||||
self.create_ram_l(x,y)
|
||||
if is_serdes(x,y):
|
||||
self.create_serdes(x,y)
|
||||
self.create_pll()
|
||||
|
|
|
|||
Loading…
Reference in New Issue